Merge pull request 'Improve HAL' (#11) from improve-hal into main

Reviewed-on: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/pulls/11

.cargo/def-config.toml

@@ -24,8 +24,7 @@ rustflags = [
   # "-C", "link-arg=-Tdefmt.x",
 
   # Can be useful for debugging.
-  "-Clink-args=-Map=app.map"
-
+  # "-Clink-args=-Map=app.map"
 ]
 
 [build]

README.md

@@ -106,3 +106,6 @@ configuration variables in your `settings.json`:
 - `"cortex-debug.gdbPath.linux"`
 - `"cortex-debug.gdbPath.windows"`
 - `"cortex-debug.gdbPath.osx"`
+
+The provided VS Code configurations also provide an integrated RTT logger, which you can access
+via the terminal at `RTT Ch:0 console`.

board-tests/Cargo.toml

@@ -15,7 +15,7 @@ embedded-hal-nb = "1"
 embedded-io = "0.6"
 
 [dependencies.va108xx-hal]
-version = "0.6"
+version = "0.7"
 path = "../va108xx-hal"
 features = ["rt"]
 

examples/simple/Cargo.toml

@@ -28,6 +28,6 @@ version = "1"
 features = ["cortex-m-systick"]
 
 [dependencies.va108xx-hal]
-version = "0.6"
+version = "0.7"
 path = "../../va108xx-hal"
 features = ["rt", "defmt"]

examples/simple/examples/pwm.rs

@@ -21,9 +21,9 @@ fn main() -> ! {
     let mut dp = pac::Peripherals::take().unwrap();
     let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
     let mut pwm = pwm::PwmPin::new(
-        (pinsa.pa3.into_funsel_1(), dp.tim3),
-        50.MHz(),
         &mut dp.sysconfig,
+        50.MHz(),
+        (pinsa.pa3.into_funsel_1(), dp.tim3),
         10.Hz(),
     );
     let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);

examples/simple/examples/rtt-log.rs

@@ -3,12 +3,14 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use panic_halt as _;
+use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
+use va108xx_hal as _;
 
 #[entry]
 fn main() -> ! {
     rtt_init_print!();
+    rprintln!("-- VA108XX RTT example --");
     let mut counter = 0;
     loop {
         rprintln!("{}: Hello, world!", counter);

examples/simple/examples/spi.rs

@@ -73,12 +73,12 @@ fn main() -> ! {
                 pinsa.pa30.into_funsel_1(),
                 pinsa.pa29.into_funsel_1(),
             );
-            let mut spia = Spi::spia(
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
                 dp.spia,
                 (sck, miso, mosi),
-                50.MHz(),
                 spi_cfg,
-                Some(&mut dp.sysconfig),
                 None,
             );
             spia.set_fill_word(FILL_WORD);
@@ -90,12 +90,12 @@ fn main() -> ! {
                 pinsb.pb8.into_funsel_2(),
                 pinsb.pb7.into_funsel_2(),
             );
-            let mut spia = Spi::spia(
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
                 dp.spia,
                 (sck, miso, mosi),
-                50.MHz(),
                 spi_cfg,
-                Some(&mut dp.sysconfig),
                 None,
             );
             spia.set_fill_word(FILL_WORD);
@@ -107,12 +107,12 @@ fn main() -> ! {
                 pinsb.pb4.into_funsel_1(),
                 pinsb.pb3.into_funsel_1(),
             );
-            let mut spib = Spi::spib(
+            let mut spib = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
                 dp.spib,
                 (sck, miso, mosi),
-                50.MHz(),
                 spi_cfg,
-                Some(&mut dp.sysconfig),
                 None,
             );
             spib.set_fill_word(FILL_WORD);
@@ -195,6 +195,10 @@ fn main() -> ! {
                     if EXAMPLE_SEL == ExampleSelect::Loopback {
                         // Can't really verify correct reply here.
                         spi.write(&[0x42]).expect("write failed");
+                        // Need small delay.. otherwise we will read back the sent byte (which we don't want here).
+                        // The write function will return as soon as all bytes were shifted out, ignoring the
+                        // reply bytes.
+                        delay.delay_us(50);
                         // Because of the loopback mode, we should get back the fill word here.
                         spi.read(&mut reply_buf[0..1]).unwrap();
                         assert_eq!(reply_buf[0], FILL_WORD);

examples/simple/examples/uart-irq-rtic.rs

@@ -65,7 +65,7 @@ mod app {
 
         let irq_cfg = IrqCfg::new(pac::interrupt::OC3, true, true);
         let (mut irq_uart, _) =
-            uart::Uart::uartb(dp.uartb, (tx, rx), 115200.Hz(), &mut dp.sysconfig, 50.MHz())
+            uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uartb, (tx, rx), 115200.Hz())
                 .into_uart_with_irq(irq_cfg, Some(&mut dp.sysconfig), Some(&mut dp.irqsel))
                 .downgrade();
         irq_uart

examples/simple/examples/uart.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     let tx = gpioa.pa9.into_funsel_2();
     let rx = gpioa.pa8.into_funsel_2();
 
-    let uarta = uart::Uart::uarta(dp.uarta, (tx, rx), 115200.Hz(), &mut dp.sysconfig, 50.MHz());
+    let uarta = uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uarta, (tx, rx), 115200.Hz());
     let (mut tx, mut rx) = uarta.split();
     writeln!(tx, "Hello World\r").unwrap();
     loop {

va108xx-hal/CHANGELOG.md

@@ -6,6 +6,14 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
+## [v0.7.0] 2024-07-04
+
+- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor
+- Replace SPI `spia`, `spib` and `spic` constructors by `new` constructor
+- Replace I2C `i2ca`, `i2cb` constructors by `new` constructor. Update constructor
+  to fail on invalid fast I2C speed system clock values
+- Renamed `gpio::pins` to `gpio::pin` and `gpio::dynpins` to `gpio::dynpin`
+
 ## [v0.6.0] 2024-06-16
 
 - Updated `embedded-hal` to v1

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.6.0"
+version = "0.7.0"
 authors = ["Robin Mueller <[email protected]>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"

va108xx-hal/README.md

@@ -4,7 +4,7 @@
 # HAL for the Vorago VA108xx MCU family
 
 This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional
-hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va108xx).
+hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx).
 
 It is the result of reading the datasheet for the device and encoding a type-safe layer over the
 raw PAC. This crate also implements traits specified by the

va108xx-hal/src/gpio/dynpins.rs → va108xx-hal/src/gpio/dynpin.rs

@@ -57,7 +57,7 @@
 //! [InvalidPinTypeError].
 
 use super::{
-    pins::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
+    pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
     reg::RegisterInterface,
 };
 use crate::{clock::FilterClkSel, pac, FunSel, IrqCfg};

va108xx-hal/src/gpio/mod.rs

@@ -3,18 +3,18 @@
 //! The implementation of this GPIO module is heavily based on the
 //! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html).
 //!
-//! This API provides two different submodules, [`mod@pins`] and [`dynpins`],
-//! representing two different ways to handle GPIO pins. The default, [`mod@pins`],
+//! This API provides two different submodules, [pin] and [dynpin],
+//! representing two different ways to handle GPIO pins. The default, [pin],
 //! is a type-level API that tracks the state of each pin at compile-time. The
-//! alternative, [`dynpins`] is a type-erased, value-level API that tracks the
+//! alternative, [dynpin] is a type-erased, value-level API that tracks the
 //! state of each pin at run-time.
 //!
 //! The type-level API is strongly preferred. By representing the state of each
 //! pin within the type system, the compiler can detect logic errors at
 //! compile-time. Furthermore, the type-level API has absolutely zero run-time
 //! cost.
 //!
-//! If needed, [`dynpins`] can be used to erase the type-level differences
+//! If needed, [dynpin] can be used to erase the type-level differences
 //! between pins. However, by doing so, pins must now be tracked at run-time,
 //! and each pin has a non-zero memory footprint.
 //!
@@ -101,10 +101,10 @@ macro_rules! common_reg_if_functions {
     };
 }
 
-pub mod dynpins;
-pub use dynpins::*;
+pub mod dynpin;
+pub use dynpin::*;
 
-pub mod pins;
-pub use pins::*;
+pub mod pin;
+pub use pin::*;
 
 mod reg;

va108xx-hal/src/gpio/pins.rs → va108xx-hal/src/gpio/pin.rs

@@ -70,7 +70,7 @@
 //! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
 //! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
 //! and [`StatefulOutputPin`].
-use super::dynpins::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
+use super::dynpin::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
 use super::reg::RegisterInterface;
 use crate::{
     pac::{Irqsel, Porta, Portb, Sysconfig},

va108xx-hal/src/gpio/reg.rs

@@ -1,5 +1,5 @@
-use super::dynpins::{self, DynGroup, DynPinId, DynPinMode};
-use super::pins::{FilterType, InterruptEdge, InterruptLevel, PinState};
+use super::dynpin::{self, DynGroup, DynPinId, DynPinMode};
+use super::pin::{FilterType, InterruptEdge, InterruptLevel, PinState};
 use super::IsMaskedError;
 use crate::clock::FilterClkSel;
 use va108xx::{ioconfig, porta};
@@ -30,7 +30,7 @@ impl From<DynPinMode> for ModeFields {
         use DynPinMode::*;
         match mode {
             Input(config) => {
-                use dynpins::DynInput::*;
+                use dynpin::DynInput::*;
                 fields.dir = false;
                 match config {
                     Floating => (),
@@ -44,7 +44,7 @@ impl From<DynPinMode> for ModeFields {
                 }
             }
             Output(config) => {
-                use dynpins::DynOutput::*;
+                use dynpin::DynOutput::*;
                 fields.dir = true;
                 match config {
                     PushPull => (),