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Upgrade to 7.2.22#2349

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Nitr0-G wants to merge 33 commits into
unicorn-engine:devfrom
Nitr0-G:dev-qemu-7.2.22
Open

Upgrade to 7.2.22#2349
Nitr0-G wants to merge 33 commits into
unicorn-engine:devfrom
Nitr0-G:dev-qemu-7.2.22

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@Nitr0-G

@Nitr0-G Nitr0-G commented Jun 27, 2026

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Update the embedded QEMU-derived runtime and target code to the 7.2.22 baseline while preserving Unicorn's reduced integration model.

This brings in the QEMU 7.2 support code needed by the fork: softfloat/int128 and helper compatibility, TCG and translator glue, updated symbol-postfix headers, target feature masks, and generated binding constants.

CPU-visible coverage was expanded across the supported targets: AArch64 SVE/SME/MTE/PMU and M-profile MVE, RISC-V RVV/RVH/bitmanip/crypto/Zfh/Sstc/PMP paths, s390x MIE/VE/Vector-FP/string/crypto paths, PPC POWER10, MIPS public modes and MSA registers, M68K, SPARC and x86 AVX/AVX2/FMA/BMI/VAES/VPCLMUL validation.

The unit test suite was extended with focused regressions for the migrated behavior, and the local MSVC test tree has been validated with full parallel CTest.

marius and others added 30 commits June 22, 2026 09:03
Fix x86 BLSI carry flag semantics.

Issue: unicorn-engine#2330
Fix x86 BZHI index boundary semantics.

Issue: unicorn-engine#2331
Fix x86 CMPXCHG accumulator update semantics.

Issue: unicorn-engine#2332
Fix x86 RET imm16 stack adjustment semantics.

Issue: unicorn-engine#2336
Fix x86 RIP-relative addressing with trailing immediates.

Issue: unicorn-engine#2335
Fix x86 PDEP 32-bit mask width handling.

Issue: unicorn-engine#2334
Fix RISC-V single-precision NaN-boxing semantics.

Issue: unicorn-engine#2314
Handle ARM CP15 c15 MRRC/MCRR as RAZ/WI for covered CPU models. Add a regression test for the reported instruction encoding.

Issue: unicorn-engine#1954
Preserve ARM IT state across continuing memory hooks.

Issue: unicorn-engine#2309
Stop RISC-V translation at the Unicorn exit address before fetching the next instruction, avoiding a spurious fetch from an unmapped following page.

unicorn-engine#1931
Update the embedded QEMU-derived runtime and target code to the 7.2.22 baseline while preserving Unicorn's reduced integration model.

This brings in the QEMU 7.2 support code needed by the fork: softfloat/int128 and helper compatibility, TCG and translator glue, updated symbol-postfix headers, target feature masks, and generated binding constants.

CPU-visible coverage was expanded across the supported targets: AArch64 SVE/SME/MTE/PMU and M-profile MVE, RISC-V RVV/RVH/bitmanip/crypto/Zfh/Sstc/PMP paths, s390x MIE/VE/Vector-FP/string/crypto paths, PPC POWER10 groups, MIPS public modes and MSA registers, M68K FPU/MSP/ColdFire behavior, SPARC register access, and x86 AVX/AVX2/FMA/BMI/VAES/VPCLMUL validation.

The unit test suite was extended with focused regressions for the migrated behavior, and the local MSVC test tree has been validated with full parallel CTest.
Keep the aarch64 backend call emitter on the reduced tree's tcg_out_call pointer ABI so ubuntu-aarch64 builds compile again.

Use concise CTest failure output in Build UC2 so parallel CI logs expose the failing test case instead of losing it inside verbose interleaved output.
Align host TCG direct jump patching with the QEMU 7.2 tc_ptr/jmp_rx/jmp_rw ABI, add missing non-goto_ptr host backend definitions, and fix PPC host TCG opcode/table drift.

Move variable target page size state out of release-mode macros that depended on a local uc variable, using arch-postfixed target_page_bits_state instead.

Fix POSIX MIPS CPU alignment and preserve microMIPS entry state, and avoid Apple JIT state asserts when virtualized macOS runners cannot report SPRR permissions.
Keep variable target page size state per Unicorn engine instead of arch-global state, while preserving the improved finalization path.

Add a public control regression that runs two ARM engines with different page sizes in the same process.
Synchronize generated code writes with instruction fetches when patching TCG direct jumps and finalizing generated code. This keeps the reduced JIT path aligned with QEMU 7.2 host cache semantics on non-coherent host caches.
Align the reduced TCG generated-code pointers with the QEMU 7.2 RX/RW address model so host backends compute branch offsets, labels, prologue addresses, and jump patches against executable addresses while still writing through writable addresses.

Use runtime MIPS guest endianness for unaligned store helpers and declare the PPC host cache flush helper used by reduced per-target builds.
Keep split-WX conversion inline in the reduced single-mapping TCG runtime so per-arch archives do not define duplicate data symbols during GNU ld links.
Pin the Zig macOS workflow to macos-14 so Zig 0.14 does not run on an unsupported macOS 26 image.
Use pthread JIT write-protection transitions directly and avoid private SPRR state probes on Apple Silicon hosts.
Nitr0-G added 3 commits June 28, 2026 00:51
Use helper typemasks when extending TCG call arguments so pointer operands are not treated as 32-bit values on aarch64 hosts. Restore s390x instruction-start metadata emission for early Unicorn exit TBs.
Avoid freeing BF16 VCVT temporaries after neon_store_reg consumes them.
Restore QEMU 7.2 ppc modulo lowering and long goto_tb reset handling.

Revalidate TLB entries after Unicorn memory callbacks that can flush or resize TLB state.
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2 participants