Use new PTP time distribution subsystem

Signed-off-by: Alex Forencich <[email protected]>
ucsdsysnet · Nov 8, 2023 · d9c39c2 · d9c39c2
1 parent 56887b8
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diff --git a/docs/source/rb/index.rst b/docs/source/rb/index.rst
@@ -78,7 +78,7 @@ The NIC register space is constructed from a linked list of register blocks.  Ea
     0x0000C040  0x00000100  :ref:`rb_sched_rr`
     0x0000C050  0x00000100  :ref:`rb_sched_ctrl_tdma`
     0x0000C060  0x00000100  :ref:`rb_tdma_sch`
-    0x0000C080  0x00000100  :ref:`rb_phc`
+    0x0000C080  0x00000200  :ref:`rb_phc`
     0x0000C081  0x00000100  :ref:`rb_phc_perout`
     0x0000C090  0x00000200  :ref:`rb_rx_queue_map`
     0x0000C100  0x00000100  :ref:`rb_gpio`

diff --git a/docs/source/rb/phc.rst b/docs/source/rb/phc.rst
diff --git a/docs/source/rb/phc_perout.rst b/docs/source/rb/phc_perout.rst
@@ -46,6 +46,8 @@ The PTP period output register block has a header with type 0x0000C081, version
 
 See :ref:`rb_overview` for definitions of the standard register block header fields.
 
+The period output module keeps track of the times for the next rising edge and next falling edge.  Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge.  If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future.  Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly.
+
 .. object:: Control
 
     The control register contains several control and status bits relating to the operation of the period output module.
@@ -77,8 +79,6 @@ See :ref:`rb_overview` for definitions of the standard register block header fie
 
     The error bit indicates that the period output module came out of lock due to the PTP clock being stepped.  The error bit is self-clearing on either reacquisition of lock or a setting change.
 
-    The period output module keeps track of the times for the next rising edge and next falling edge.  Initially, it starts with the specified start time for the rising edge, and start time plus width for the falling edge.  If the computed next rising edge time is in the past, the period will be added and it will be checked again, repeating this process until the next rising edge is in the future.  Note that the period is added once per clock cycle, so it is recommended to compute a start time that is close to the current time, particularly when using a small period setting, so that the period output module can lock quickly.
-
 .. object:: Start time
 
     The start time registers determine the absolute start time for the output waveform (rising edge), with all values latched coincident with writing the upper 32 bits of the seconds field.

diff --git a/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v b/fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
@@ -314,13 +314,16 @@ module mqnic_app_block #
     input  wire                                           ptp_clk,
     input  wire                                           ptp_rst,
     input  wire                                           ptp_sample_clk,
+    input  wire                                           ptp_td_sd,
     input  wire                                           ptp_pps,
     input  wire                                           ptp_pps_str,
-    input  wire [PTP_TS_WIDTH-1:0]                        ptp_ts_96,
-    input  wire                                           ptp_ts_step,
+    input  wire                                           ptp_sync_locked,
+    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_rel,
+    input  wire                                           ptp_sync_ts_rel_step,
+    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_tod,
+    input  wire                                           ptp_sync_ts_tod_step,
     input  wire                                           ptp_sync_pps,
-    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_96,
-    input  wire                                           ptp_sync_ts_step,
+    input  wire                                           ptp_sync_pps_str,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_locked,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_error,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_pulse,

diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
@@ -60,8 +60,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v

diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
                     ifg=12, speed=eth_speed
                 )
 
@@ -1015,8 +1015,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
-        os.path.join(eth_rtl_dir, "ptp_clock.v"),
-        os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(eth_rtl_dir, "lfsr.v"),
         os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"),

diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v
@@ -314,13 +314,16 @@ module mqnic_app_block #
     input  wire                                           ptp_clk,
     input  wire                                           ptp_rst,
     input  wire                                           ptp_sample_clk,
+    input  wire                                           ptp_td_sd,
     input  wire                                           ptp_pps,
     input  wire                                           ptp_pps_str,
-    input  wire [PTP_TS_WIDTH-1:0]                        ptp_ts_96,
-    input  wire                                           ptp_ts_step,
+    input  wire                                           ptp_sync_locked,
+    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_rel,
+    input  wire                                           ptp_sync_ts_rel_step,
+    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_tod,
+    input  wire                                           ptp_sync_ts_tod_step,
     input  wire                                           ptp_sync_pps,
-    input  wire [PTP_TS_WIDTH-1:0]                        ptp_sync_ts_96,
-    input  wire                                           ptp_sync_ts_step,
+    input  wire                                           ptp_sync_pps_str,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_locked,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_error,
     input  wire [PTP_PEROUT_COUNT-1:0]                    ptp_perout_pulse,

diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -58,8 +58,8 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_ctrl_tx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
 VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
-VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
 VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
 VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v

diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -308,14 +308,14 @@ def __init__(self, dut, msix_count=32):
                     tx_clk=iface.port[k].port_tx_clk,
                     tx_rst=iface.port[k].port_tx_rst,
                     tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
-                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
+                    tx_ptp_time=iface.port[k].port_tx_ptp_ts_tod,
                     tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
                     tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
                     tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
                     rx_clk=iface.port[k].port_rx_clk,
                     rx_rst=iface.port[k].port_rx_rst,
                     rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
-                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
+                    rx_ptp_time=iface.port[k].port_rx_ptp_ts_tod,
                     ifg=12, speed=eth_speed
                 )
 
@@ -814,8 +814,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(eth_rtl_dir, "mac_ctrl_tx.v"),
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_rx.v"),
         os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
-        os.path.join(eth_rtl_dir, "ptp_clock.v"),
-        os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
+        os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
         os.path.join(eth_rtl_dir, "ptp_perout.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar.v"),
         os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),