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fpga/common: Move scheduler port allocation
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Signed-off-by: Alex Forencich <[email protected]>
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alexforencich committed Feb 29, 2024
1 parent 2a6465c commit 4c5dbdf
Showing 1 changed file with 6 additions and 1 deletion.
7 changes: 6 additions & 1 deletion fpga/common/tb/mqnic.py
Original file line number Diff line number Diff line change
Expand Up @@ -1426,7 +1426,7 @@ def __init__(self, interface, index, port):
self.port_up = False

self.port = port
self.sched_port = interface.alloc_sched_port()
self.sched_port = None

self.txq_count = min(interface.txq_res.get_count(), 4)
self.rxq_count = min(interface.rxq_res.get_count(), 4)
Expand All @@ -1450,6 +1450,8 @@ async def open(self):
if self.port_up:
return

self.sched_port = self.interface.alloc_sched_port()

for k in range(self.rxq_count):
cq = self.interface.create_cq()
await cq.open(self.interface.eq[k % len(self.interface.eq)], 1024)
Expand Down Expand Up @@ -1550,6 +1552,9 @@ async def close(self):

await self.ports[0].set_tx_ctrl(0)

self.interface.free_sched_port(self.sched_port)
self.sched_port = None

async def start_xmit(self, skb, tx_ring=None, csum_start=None, csum_offset=None):
if not self.port_up:
return
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