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fpga/mqnic/Alveo: Rework AU200 clocking
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Signed-off-by: Alex Forencich <[email protected]>
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@alexforencich
alexforencich committed Nov 16, 2023
1 parent 534cd37 commit 439f8ab
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Showing 20 changed files with 216 additions and 102 deletions.
4 changes: 0 additions & 4 deletions fpga/mqnic/Alveo/fpga_100g/cfgmclk.xdc
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile
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Expand Up @@ -117,7 +117,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au200.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile
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Expand Up @@ -124,7 +124,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au200.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au250.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile
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Expand Up @@ -124,7 +124,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au250.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_vcu1525.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
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1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile
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Expand Up @@ -121,7 +121,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_vcu1525.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
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16 changes: 12 additions & 4 deletions fpga/mqnic/Alveo/fpga_100g/fpga_au200.xdc
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Expand Up @@ -22,22 +22,30 @@ set_operating_conditions -design_power_budget 160
# 300 MHz (DDR 0)
set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]

set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -quiet clk_300mhz_0_int]

# 300 MHz (DDR 1)
set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]

set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -quiet clk_300mhz_1_int]

# 300 MHz (DDR 2)
set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]

set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -quiet clk_300mhz_2_int]

# 300 MHz (DDR 3)
set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]

set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_nets -quiet clk_300mhz_3_int]

# SI570 user clock
#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p]
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1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/ip/ddr4_0.tcl
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Expand Up @@ -2,6 +2,7 @@
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0

set_property -dict [list \
CONFIG.System_Clock {No_Buffer} \
CONFIG.C0.DDR4_AxiSelection {true} \
CONFIG.C0.DDR4_AxiDataWidth {512} \
CONFIG.C0.DDR4_AxiIDWidth {8} \
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132 changes: 95 additions & 37 deletions fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
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Original file line number Diff line number Diff line change
Expand Up @@ -313,9 +313,8 @@ parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
wire pcie_user_clk;
wire pcie_user_reset;

wire cfgmclk_int;

wire clk_161mhz_ref_int;
wire clk_300mhz_0_ibufg;
wire clk_300mhz_0_int;

wire clk_50mhz_mmcm_out;
wire clk_125mhz_mmcm_out;
Expand All @@ -332,22 +331,38 @@ wire mmcm_rst;
wire mmcm_locked;
wire mmcm_clkfb;

IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_300mhz_0_ibufg_inst (
.O (clk_300mhz_0_ibufg),
.I (clk_300mhz_0_p),
.IB (clk_300mhz_0_n)
);

BUFG
clk_300mhz_0_bufg_inst (
.I(clk_300mhz_0_ibufg),
.O(clk_300mhz_0_int)
);

// MMCM instance
// 161.13 MHz in, 50 MHz + 125 MHz out
// 300 MHz in, 125 MHz + 50 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 128, D = 15 sets Fvco = 1375 MHz (in range)
// Divide by 27.5 to get output frequency of 50 MHz
// Divide by 11 to get output frequency of 125 MHz
// M = 10, D = 3 sets Fvco = 1000 MHz
// Divide by 8 to get output frequency of 125 MHz
// Divide by 20 to get output frequency of 50 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(27.5),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(11),
.CLKOUT1_DIVIDE(20),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DIVIDE(3),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
Expand All @@ -362,22 +377,22 @@ MMCME4_BASE #(
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(128),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(15),
.DIVCLK_DIVIDE(3),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.CLKIN1_PERIOD(3.333),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKIN1(clk_300mhz_0_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_50mhz_mmcm_out),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk_125mhz_mmcm_out),
.CLKOUT1(clk_50mhz_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
Expand Down Expand Up @@ -507,12 +522,10 @@ flash_sync_signal_inst (
);

// startupe3 instance
wire cfgmclk;

STARTUPE3
startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.CFGMCLK(),
.DI(qspi_dq_int),
.DO(qspi_dq_o_reg),
.DTS(~qspi_dq_oe_reg),
Expand All @@ -530,12 +543,6 @@ startupe3_inst (
.USRDONETS(1'b1)
);

BUFG
cfgmclk_bufg_inst (
.I(cfgmclk),
.O(cfgmclk_int)
);

// FPGA boot
wire fpga_boot;

Expand Down Expand Up @@ -809,11 +816,11 @@ endgenerate
reg qsfp_refclk_reset_reg = 1'b1;
reg sys_reset_reg = 1'b1;

reg [9:0] reset_timer_reg = 0;
reg [11:0] reset_timer_reg = 0;

assign mmcm_rst = sys_reset_reg | pcie_user_reset;

always @(posedge cfgmclk_int) begin
always @(posedge clk_300mhz_0_int) begin
if (&reset_timer_reg) begin
if (qsfp_refclk_reset_reg) begin
qsfp_refclk_reset_reg <= 1'b0;
Expand Down Expand Up @@ -1166,8 +1173,6 @@ wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;

assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;

IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
Expand Down Expand Up @@ -1482,8 +1487,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
end

ddr4_0 ddr4_c0_inst (
.c0_sys_clk_p(clk_300mhz_0_p),
.c0_sys_clk_n(clk_300mhz_0_n),
.c0_sys_clk_i(clk_300mhz_0_int),
.sys_rst(ddr4_rst_reg),

.c0_init_calib_complete(ddr_status[0 +: 1]),
Expand Down Expand Up @@ -1608,6 +1612,25 @@ assign ddr_status = 0;

end

wire clk_300mhz_1_ibufg;
wire clk_300mhz_1_int;

IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_300mhz_1_ibufg_inst (
.O (clk_300mhz_1_ibufg),
.I (clk_300mhz_1_p),
.IB (clk_300mhz_1_n)
);

BUFG
clk_300mhz_1_bufg_inst (
.I(clk_300mhz_1_ibufg),
.O(clk_300mhz_1_int)
);

if (DDR_ENABLE && DDR_CH > 1) begin

reg ddr4_rst_reg = 1'b1;
Expand All @@ -1621,8 +1644,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
end

ddr4_0 ddr4_c1_inst (
.c0_sys_clk_p(clk_300mhz_1_p),
.c0_sys_clk_n(clk_300mhz_1_n),
.c0_sys_clk_i(clk_300mhz_1_int),
.sys_rst(ddr4_rst_reg),

.c0_init_calib_complete(ddr_status[1 +: 1]),
Expand Down Expand Up @@ -1730,6 +1752,25 @@ OBUFTDS ddr4_c1_ck_obuftds_inst (

end

wire clk_300mhz_2_ibufg;
wire clk_300mhz_2_int;

IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_300mhz_2_ibufg_inst (
.O (clk_300mhz_2_ibufg),
.I (clk_300mhz_2_p),
.IB (clk_300mhz_2_n)
);

BUFG
clk_300mhz_2_bufg_inst (
.I(clk_300mhz_2_ibufg),
.O(clk_300mhz_2_int)
);

if (DDR_ENABLE && DDR_CH > 2) begin

reg ddr4_rst_reg = 1'b1;
Expand All @@ -1743,8 +1784,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
end

ddr4_0 ddr4_c2_inst (
.c0_sys_clk_p(clk_300mhz_2_p),
.c0_sys_clk_n(clk_300mhz_2_n),
.c0_sys_clk_i(clk_300mhz_2_int),
.sys_rst(ddr4_rst_reg),

.c0_init_calib_complete(ddr_status[2 +: 1]),
Expand Down Expand Up @@ -1852,6 +1892,25 @@ OBUFTDS ddr4_c2_ck_obuftds_inst (

end

wire clk_300mhz_3_ibufg;
wire clk_300mhz_3_int;

IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_300mhz_3_ibufg_inst (
.O (clk_300mhz_3_ibufg),
.I (clk_300mhz_3_p),
.IB (clk_300mhz_3_n)
);

BUFG
clk_300mhz_3_bufg_inst (
.I(clk_300mhz_3_ibufg),
.O(clk_300mhz_3_int)
);

if (DDR_ENABLE && DDR_CH > 3) begin

reg ddr4_rst_reg = 1'b1;
Expand All @@ -1865,8 +1924,7 @@ always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
end

ddr4_0 ddr4_c3_inst (
.c0_sys_clk_p(clk_300mhz_3_p),
.c0_sys_clk_n(clk_300mhz_3_n),
.c0_sys_clk_i(clk_300mhz_3_int),
.sys_rst(ddr4_rst_reg),

.c0_init_calib_complete(ddr_status[3 +: 1]),
Expand Down
4 changes: 0 additions & 4 deletions fpga/mqnic/Alveo/fpga_25g/cfgmclk.xdc
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This file was deleted.

1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au200.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
Expand Down
1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au200.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
Expand Down
1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au250.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
Expand Down
1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_au250.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
Expand Down
1 change: 0 additions & 1 deletion fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga_au200.xdc
XDC_FILES += placement_vcu1525.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
Expand Down
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