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Add ETH_RS_FEC_ENABLE to config.tcl for UltraScale+ 100G designs
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Signed-off-by: Alex Forencich <[email protected]>
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@alexforencich
alexforencich committed May 4, 2024
1 parent b10d5d2 commit 37f2607
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Showing 37 changed files with 60 additions and 23 deletions.
1 change: 1 addition & 0 deletions fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
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Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -779,7 +780,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -953,7 +954,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
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Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1014,7 +1015,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp_0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1188,7 +1189,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp_1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU280/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -159,6 +159,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU280_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -159,6 +159,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU50/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU50_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU55N/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_AU55N_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
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Original file line number Diff line number Diff line change
Expand Up @@ -133,6 +133,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1223,7 +1224,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1355,7 +1356,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
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Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1102,7 +1103,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1230,7 +1231,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
3 changes: 2 additions & 1 deletion fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1043,7 +1044,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1048,7 +1049,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1173,7 +1174,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
5 changes: 3 additions & 2 deletions fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
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Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1001,7 +1002,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1140,7 +1141,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp2_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "4"
dict set params AXIS_ETH_RX_PIPELINE "4"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
9 changes: 5 additions & 4 deletions fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,7 @@ module fpga #
parameter AXIS_ETH_RX_PIPELINE = 4,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
parameter ETH_RX_CLK_FROM_TX = 0,
parameter ETH_RS_FEC_ENABLE = 1,

// Statistics counter subsystem
parameter STAT_ENABLE = 1,
Expand Down Expand Up @@ -1105,7 +1106,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp0_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1279,7 +1280,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp1_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1453,7 +1454,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp2_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down Expand Up @@ -1627,7 +1628,7 @@ cmac_gty_wrapper #(
.TX_SERDES_PIPELINE(0),
.RX_SERDES_PIPELINE(0),
.RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
.RS_FEC_ENABLE(1)
.RS_FEC_ENABLE(ETH_RS_FEC_ENABLE)
)
qsfp3_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
Expand Down
1 change: 1 addition & 0 deletions fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_RX_CLK_FROM_TX "0"
dict set params ETH_RS_FEC_ENABLE "1"

# Statistics counter subsystem
dict set params STAT_ENABLE "1"
Expand Down
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