Resolves #29. Still WIP:

• Update CSR implementation to match latest spec
• Unify hex files for Scala and verilator tests
• Modify the magic memory model to load program at DRAM base
• Debug test failures manually via waveform
• Modify the verilator testbench to snoop the dcache request bus to look for tohost writes
• Modify Makefile to compile and use tests in riscv-tests
• Support "syscall" API used in riscv-tests/benchmarks