Queue is not getting synthesized

Hi, 

I am using Synopsys tool to synthesize a verilog netlist generated from Chisel implementation. 
Tool is not able to map any library cells to reg_files of Queue creating sequential generated structures (named SEQGEN in synthesized netlist)

PS:I have checked completeness of library used.  

Has anybody seen similar issue?

Thanks & Regards,
Preyas
