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Revisions

  • 'Generating Verilog' example uses 'Adder' not 'GCD'.

    @ucbjrl ucbjrl committed Oct 19, 2017
    16e7640

  • Update 'Generating Verilog' instructions - --backend specification.

    @ucbjrl ucbjrl committed Oct 19, 2017
    ea3f92c

  • Created Frequently Asked Questions (markdown)

    @chick chick committed Apr 27, 2017
    b0b4ee8