A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

80186 compatible SystemVerilog CPU core and FPGA reference design

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

A Forth CPU and System on a Chip, based on the J1, written in VHDL

🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Mostly AVR compatible FPGA soft-core

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

Soft-core uController POC using the risc16f84 pic clone and sdcc c-compiler

A 16 bit softcore processor implemented in VHDL

Trabalho de conclusão de curso de título Integração de ramais analógicos com FPGA utilizando processador softcore

Trying to implement a soft core SoC

A cycle-accurate VHDL model for MCS-48 and UPI devices

Set of basic image processing systems implemented for learning purposes.

Implementation of a soft-core CPU and an assembler

A RISC/CISC 32 bit softcore processor in VHDL

PIC16F84 soft-core RTL

EC16-CPU running ECMON @ 20MHz on an ICE40UP5K-SG48 (ICY40-Board)