This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.

A CPU Simulator

Processor Design of RV32I 5-Stage Pipelined CPU

RISC-V RV32I 5-stage pipelined processor implemented in SystemVerilog with RTL design, testbench, and hex-based instruction memory.

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

A custom 5-stage pipelined CPU implemented on FPGA and based on the VeSPA ISA, designed for educational exploration of computer architecture and digital design.