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A4091 improvements #227

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A4091 improvements #227

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f793178
lsi53c710: fix register access mapping
reinauer Aug 19, 2022
8641617
A4091: Allow 32 and 64KB ROMs
reinauer Aug 19, 2022
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3 changes: 2 additions & 1 deletion ncr_scsi.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@
#include "scsi.h"
#include "filesys.h"
#include "zfile.h"
#include "zarchive.h"
#include "blkdev.h"
#include "cpuboard.h"
#include "qemuvga/qemuuaeglue.h"
Expand All @@ -37,7 +38,7 @@

#define A4091_ROM_VECTOR 0x0200
#define A4091_ROM_OFFSET 0x0000
#define A4091_ROM_SIZE 32768
#define A4091_ROM_SIZE (z->size)
#define A4091_ROM_MASK (A4091_ROM_SIZE - 1)

#define A4091_IO_OFFSET 0x00800000
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4 changes: 2 additions & 2 deletions qemuvga/lsi53c710.cpp
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Expand Up @@ -1643,7 +1643,7 @@ static uint8_t lsi_reg_readb2(LSIState710 *s, int offset)
case addr + 2: return (s->name >> 16) & 0xff; \
case addr + 3: return (s->name >> 24) & 0xff;

switch (offset)
switch (offset & 0x3f)
{
case 0x00: /* SCNTL0 */
return s->scntl0;
Expand Down Expand Up @@ -1775,7 +1775,7 @@ static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val)
#ifdef DEBUG_LSI_REG
DPRINTF("Write reg %x = %02x\n", offset, val);
#endif
switch (offset) {
switch (offset & 0x3f) {
case 0x00: /* SCNTL0 */
s->scntl0 = val;
if (val & LSI_SCNTL0_START) {
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2 changes: 2 additions & 0 deletions rommgr.cpp
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Expand Up @@ -446,6 +446,8 @@ static struct romdata roms[] = {
0x7e12a120, 0xa411d572,0x6801dc44,0x3d41428f,0x382ae3d5,0x6f44ef27 },
{ _T("A4091 v40.13"), 40, 13, 40, 13, _T("A4091\0"), 32768, 58, 0, 0, ROMTYPE_A4091, 0, 0, _T("391592-02"),
0x54cb9e85, 0x3CE66919,0xF6FD6797,0x4923A12D,0x91B730F1,0xFFB4A7BA },
{ _T("A4091 v42.23"), 42, 23, 42, 23, _T("A4091\0"), 65536, 58, 0, 0, ROMTYPE_A4091, 0, 0, _T("391592-03"),
0xffffffff, 0, 0, 0, 0, 0 },

{ _T("SupraDrive AMAB6"), 3, 8, 3, 8, _T("SUPRA\0"), 16384, 121, 0, 0, ROMTYPE_SUPRA, 0, 0, _T("AMAB6"),
0xf40bd349, 0x82168556,0x07525067,0xe9263431,0x1fb9c347,0xe737f247 },
Expand Down