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Add 18 register support for SMC and SVC calls for AArch64 platforms #10685

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@kuqin12 kuqin12 commented Jan 27, 2025

Description

Current SMC and SVC only supports up to 8 registers.

However, the FF-A spec has definition for FFA direct request 2 which could use up to 18 registers.

This change is added to support such use case.

  • Breaking change?
    • Breaking change - Does this PR cause a break in build or boot behavior?
    • Examples: Does it add a new library class or move a module to a different repo.
  • Impacts security?
    • Security - Does this PR have a direct security impact?
    • Examples: Crypto algorithm change or buffer overflow fix.
  • Includes tests?
    • Tests - Does this PR include any explicit test code?
    • Examples: Unit tests or integration tests.

How This Was Tested

This was tested on QEMU SBSA and booted to Windows

Integration Instructions

N/A

This change updated the ARM SMC call to support all x0-x17 registers.

Signed-off-by: Kun Qin <[email protected]>
This change updated the ARM SVC call to support all x0-x17 registers.

Signed-off-by: Kun Qin <[email protected]>
This change expands the support of FF-A direct message 2 call to use the
full 18 registers.

Signed-off-by: Kun Qin <[email protected]>
This change added the support for using 18 registers when FF-A
DIRECT_REQ2 is used to communicate with MM core.

This change was tested on QEMU SBSA and booted to Windows.

Signed-off-by: Kun Qin <[email protected]>
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