A RISC-V SoC on Terasic DE10-NANO
- Hbird E203 form Nuclei Technology
- Ported the code form LiChee-Tang
- 16Mhz clock input now(can works higher)
- 6927 LAMs and about 65Kb block ram now (maybe less)
- mask-rom boot default, and jump to itcm ram 0x80000000
- LED0 and LED2 blink default
- change the pll and ram ip for intel FPGA
- Write the LED-Blink ASM Code for E203
- Build the binary and make a mif(hex) file for itcm ram
- some timing check by signaltap and verdi simulation
- write the binary to itcam hex tools
- add led C code
- add hbird-sdk runtime (testing)
- add a simple C-based RISC-V simulator that can run led blink binary
- update the ftdi script for e203 debug with ft2232hl tools (upload the binary to itcm, then run openocd and gdb)
riscv-none-embed-gcc -march=rv32i -mabi=ilp32 -Tlink_itcm.lds -nostartfiles -o led.elf start.S main.c
riscv-none-embed-objcopy -O binary led.elf led.bin
../../../tools/bin2ihex led.bin > led.hex
cd de10-nano-riscv/hbird-sdk
export RISCV_OPENOCD= path to openocd (eg./opt/xpack-openocd-0.10.0-14/bin)
export RISCV_PATH= path to risc-v gcc path (eg./opt/riscv-none-gcc/7.2.0-2-20180111-2230)
make dasm PROGRAM=hello_world DOWNLOAD=itcm USE_NANO=1 NANO_PFLOAT=0
make upload PROGRAM=hello_world DOWNLOAD=itcm
make run_openocd PROGRAM=hello_world DOWNLOAD=itcm
open a new terminal
cd de10-nano-riscv/hbird-sdk
export RISCV_OPENOCD= path to openocd (eg./opt/xpack-openocd-0.10.0-14/bin)
export RISCV_PATH= path to risc-v gcc path (eg./opt/riscv-none-gcc/7.2.0-2-20180111-2230)
make run_gdb PROGRAM=hello_world DWONLOAD=itcm
(gdb)
break main
jump main
l
n
here is the riscv-none-gcc link
brabect1's e200_opensource repo
- install verilator and gtkwave
- make build test-rv32ui-p-xori cflags='-DVCDTRACE=1'
- gtkwave dump.vcd