Merge branch 'espressif:master' into master

components/esp_driver_i2s/i2s_common.c

@@ -25,6 +25,7 @@
 #include "soc/soc_caps.h"
 #include "hal/gpio_hal.h"
 #include "hal/i2s_hal.h"
+#include "hal/dma_types.h"
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
@@ -63,8 +64,12 @@
 #include "esp_memory_utils.h"
 
 /* The actual max size of DMA buffer is 4095
- * Set 4092 here to align with 4-byte, so that the position of the slot data in the buffer will be relatively fixed */
-#define I2S_DMA_BUFFER_MAX_SIZE     (4092)
+ * Reserve several bytes for alignment, so that the position of the slot data in the buffer will be relatively fixed */
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#define I2S_DMA_BUFFER_MAX_SIZE     DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED
+#else
+#define I2S_DMA_BUFFER_MAX_SIZE     DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED
+#endif  // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 
 static const char *TAG = "i2s_common";
 
@@ -377,7 +382,7 @@ uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uin
                  ", bufsize = %"PRIu32, bufsize / bytes_per_frame, alignment, bufsize);
     }
 #endif
-    /* Limit DMA buffer size if it is out of range (DMA buffer limitation is 4092 bytes) */
+    /* Limit DMA buffer size if it is out of range */
     if (bufsize > I2S_DMA_BUFFER_MAX_SIZE) {
         uint32_t frame_num = I2S_DMA_BUFFER_MAX_SIZE / bytes_per_frame;
         bufsize = frame_num * bytes_per_frame;

components/esp_driver_i2s/i2s_std.c

@@ -39,6 +39,9 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std
         clk_info->bclk = rate * handle->total_slot * slot_bits;
         clk_info->mclk = rate * clk_cfg->mclk_multiple;
         clk_info->bclk_div = clk_info->mclk / clk_info->bclk;
+        if (clk_info->mclk % clk_info->bclk != 0) {
+            ESP_LOGW(TAG, "the current mclk multiple cannot perform integer division (slot_num: %"PRIu32", slot_bits: %"PRIu32")", handle->total_slot, slot_bits);
+        }
     } else {
         /* For slave mode, mclk >= bclk * 8, so fix bclk_div to 2 first */
         clk_info->bclk_div = 8;

components/esp_driver_i2s/i2s_tdm.c

@@ -46,6 +46,9 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm
             clk_info->mclk = clk_info->bclk * clk_info->bclk_div;
             ESP_LOGW(TAG, "the current mclk multiple is too small, adjust the mclk multiple to %"PRIu32, clk_info->mclk / rate);
         }
+        if (clk_info->mclk % clk_info->bclk != 0) {
+            ESP_LOGW(TAG, "the current mclk multiple cannot perform integer division (slot_num: %"PRIu32", slot_bits: %"PRIu32")", handle->total_slot, slot_bits);
+        }
     } else {
         if (clk_cfg->bclk_div < 8) {
             ESP_LOGW(TAG, "the current bclk division is too small, adjust the bclk division to 8");

components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c

@@ -14,6 +14,7 @@
 #include "sdkconfig.h"
 #include "driver/gpio.h"
 #include "hal/gpio_hal.h"
+#include "hal/dma_types.h"
 #include "esp_private/gpio.h"
 #include "esp_err.h"
 #include "esp_attr.h"
@@ -841,17 +842,25 @@ TEST_CASE("I2S_package_lost_test", "[i2s]")
 {
     /* Steps of calculate appropriate parameters of I2S buffer:
      * Known by user: sample_rate = 144k, data_bit_width = 32, slot_num = 2, polling_cycle = 10 ms
-     * 1. dma_buffer_size = dma_frame_num * slot_num * data_bit_width / 8 <= 4092
-     *    dma_frame_num <= 511, dma_frame_num is as big as possible.
+     * 1. dma_buffer_size = dma_frame_num * slot_num * data_bit_width / 8 <= DMA_MAX_ALIGNED_SIZE
+     *    dma_frame_num <= DMA_MAX_ALIGNED_SIZE / data_bit_width / slot_num * 8, dma_frame_num is as big as possible.
      *    interrupt_interval = dma_frame_num / sample_rate = 3.549 ms
      * 2. dma_desc_num > polling_cycle / interrupt_interval = cell(2.818) = 3
-     * 3. recv_buffer_size > dma_desc_num * dma_buffer_size = 3 * 4092 = 12276 bytes */
-#define TEST_RECV_BUF_LEN   12276
+     * 3. recv_buffer_size > dma_desc_num * dma_buffer_size = 3 * DMA_MAX_ALIGNED_SIZE */
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#define TEST_RECV_BUF_LEN   (3 * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED)
+#else
+#define TEST_RECV_BUF_LEN   (3 * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED)
+#endif
     i2s_chan_handle_t rx_handle;
 
     i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_AUTO, I2S_ROLE_MASTER);
     chan_cfg.dma_desc_num = 3;
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+    chan_cfg.dma_frame_num = 504;
+#else
     chan_cfg.dma_frame_num = 511;
+#endif
     i2s_std_config_t std_cfg = {
         .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(SAMPLE_RATE),
         .slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),

components/esp_driver_sdmmc/include/driver/sdmmc_host.h

@@ -94,6 +94,7 @@ esp_err_t sdmmc_host_init(void);
  * @return
  *      - ESP_OK on success
  *      - ESP_ERR_INVALID_STATE if host has not been initialized using sdmmc_host_init
+ *      - ESP_ERR_INVALID_ARG if GPIO pins from slot_config are not valid
  */
 esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config);
 

components/esp_driver_sdmmc/src/sdmmc_host.c

@@ -46,12 +46,19 @@
 #define SDMMC_CLK_SRC_ATOMIC()
 #endif
 
+static const char *TAG = "sdmmc_periph";
+
 #define SLOT_CHECK(slot_num) \
 if (slot_num < 0 || slot_num >= SOC_SDMMC_NUM_SLOTS) { \
     return ESP_ERR_INVALID_ARG; \
 }
 
-static const char *TAG = "sdmmc_periph";
+#define GPIO_NUM_CHECK(_gpio_num) \
+if (!GPIO_IS_VALID_GPIO(_gpio_num)) { \
+    esp_err_t _err = ESP_ERR_INVALID_ARG; \
+    ESP_LOGE(TAG, "%s: Invalid GPIO number %d, returned 0x%x", __func__, _gpio_num, _err); \
+    return _err; \
+}
 
 /**
  * Slot contexts
@@ -580,15 +587,16 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
 
     // Configure pins
     const sdmmc_slot_info_t *slot_info = &sdmmc_slot_info[slot];
+    sdmmc_slot_io_info_t *slot_gpio = &s_host_ctx.slot_ctx[slot].slot_gpio_num;
 
     if (slot_width == SDMMC_SLOT_WIDTH_DEFAULT) {
         slot_width = slot_info->width;
     } else if (slot_width > slot_info->width) {
         return ESP_ERR_INVALID_ARG;
     }
     s_host_ctx.slot_ctx[slot].slot_width = slot_width;
-    s_host_ctx.slot_ctx[slot].slot_gpio_num.cd = gpio_cd;
-    s_host_ctx.slot_ctx[slot].slot_gpio_num.wp = gpio_wp;
+    slot_gpio->cd = gpio_cd;
+    slot_gpio->wp = gpio_wp;
 
     bool pin_not_set = s_check_pin_not_set(slot_config);
     //SD driver behaviour is: all pins not defined == using iomux
@@ -608,67 +616,86 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
 #if SOC_SDMMC_USE_GPIO_MATRIX
     if (use_gpio_matrix) {
         /* Save pin configuration for this slot */
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.clk = slot_config->clk;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.cmd = slot_config->cmd;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d0 = slot_config->d0;
+        slot_gpio->clk = slot_config->clk;
+        slot_gpio->cmd = slot_config->cmd;
+        slot_gpio->d0 = slot_config->d0;
         /* Save d1 even in 1-line mode, it might be needed for SDIO INT line */
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d1 = slot_config->d1;
+        slot_gpio->d1 = slot_config->d1;
         if (slot_width >= 4) {
-            s_host_ctx.slot_ctx[slot].slot_gpio_num.d2 = slot_config->d2;
+            slot_gpio->d2 = slot_config->d2;
         }
         /* Save d3 even for 1-line mode, as it needs to be set high */
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d3 = slot_config->d3;
+        slot_gpio->d3 = slot_config->d3;
         if (slot_width >= 8) {
-            s_host_ctx.slot_ctx[slot].slot_gpio_num.d4 = slot_config->d4;
-            s_host_ctx.slot_ctx[slot].slot_gpio_num.d5 = slot_config->d5;
-            s_host_ctx.slot_ctx[slot].slot_gpio_num.d6 = slot_config->d6;
-            s_host_ctx.slot_ctx[slot].slot_gpio_num.d7 = slot_config->d7;
+            slot_gpio->d4 = slot_config->d4;
+            slot_gpio->d5 = slot_config->d5;
+            slot_gpio->d6 = slot_config->d6;
+            slot_gpio->d7 = slot_config->d7;
         }
     } else
 #endif  //#if SOC_SDMMC_USE_GPIO_MATRIX
     {
         /* init pin configuration for this slot */
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.clk = sdmmc_slot_gpio_num[slot].clk;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.cmd = sdmmc_slot_gpio_num[slot].cmd;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d0 = sdmmc_slot_gpio_num[slot].d0;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d1 = sdmmc_slot_gpio_num[slot].d1;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d2 = sdmmc_slot_gpio_num[slot].d2;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d3 = sdmmc_slot_gpio_num[slot].d3;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d4 = sdmmc_slot_gpio_num[slot].d4;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d5 = sdmmc_slot_gpio_num[slot].d5;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d6 = sdmmc_slot_gpio_num[slot].d6;
-        s_host_ctx.slot_ctx[slot].slot_gpio_num.d7 = sdmmc_slot_gpio_num[slot].d7;
+        slot_gpio->clk = sdmmc_slot_gpio_num[slot].clk;
+        slot_gpio->cmd = sdmmc_slot_gpio_num[slot].cmd;
+        slot_gpio->d0 = sdmmc_slot_gpio_num[slot].d0;
+        slot_gpio->d1 = sdmmc_slot_gpio_num[slot].d1;
+        slot_gpio->d2 = sdmmc_slot_gpio_num[slot].d2;
+        slot_gpio->d3 = sdmmc_slot_gpio_num[slot].d3;
+        slot_gpio->d4 = sdmmc_slot_gpio_num[slot].d4;
+        slot_gpio->d5 = sdmmc_slot_gpio_num[slot].d5;
+        slot_gpio->d6 = sdmmc_slot_gpio_num[slot].d6;
+        slot_gpio->d7 = sdmmc_slot_gpio_num[slot].d7;
     }
 
     bool pullup = slot_config->flags & SDMMC_SLOT_FLAG_INTERNAL_PULLUP;
     if (pullup) {
         sdmmc_host_pullup_en_internal(slot, s_host_ctx.slot_ctx[slot].slot_width);
     }
 
-    configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.clk, sdmmc_slot_gpio_sig[slot].clk, GPIO_MODE_OUTPUT, "clk", use_gpio_matrix);
-    configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.cmd, sdmmc_slot_gpio_sig[slot].cmd, GPIO_MODE_INPUT_OUTPUT, "cmd", use_gpio_matrix);
-    configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d0, sdmmc_slot_gpio_sig[slot].d0, GPIO_MODE_INPUT_OUTPUT, "d0", use_gpio_matrix);
+    if (slot_width >= 1) {
+        GPIO_NUM_CHECK(slot_gpio->clk);
+        GPIO_NUM_CHECK(slot_gpio->cmd);
+        GPIO_NUM_CHECK(slot_gpio->d0);
+    }
+    if (slot_width >= 4) {
+        GPIO_NUM_CHECK(slot_gpio->d1);
+        GPIO_NUM_CHECK(slot_gpio->d2);
+        GPIO_NUM_CHECK(slot_gpio->d3);
+    }
+    if (slot_width == 8) {
+        GPIO_NUM_CHECK(slot_gpio->d4);
+        GPIO_NUM_CHECK(slot_gpio->d5);
+        GPIO_NUM_CHECK(slot_gpio->d6);
+        GPIO_NUM_CHECK(slot_gpio->d7);
+    }
+
+    configure_pin(slot_gpio->clk, sdmmc_slot_gpio_sig[slot].clk, GPIO_MODE_OUTPUT, "clk", use_gpio_matrix);
+    configure_pin(slot_gpio->cmd, sdmmc_slot_gpio_sig[slot].cmd, GPIO_MODE_INPUT_OUTPUT, "cmd", use_gpio_matrix);
+    configure_pin(slot_gpio->d0, sdmmc_slot_gpio_sig[slot].d0, GPIO_MODE_INPUT_OUTPUT, "d0", use_gpio_matrix);
 
     if (slot_width >= 4) {
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d1, sdmmc_slot_gpio_sig[slot].d1, GPIO_MODE_INPUT_OUTPUT, "d1", use_gpio_matrix);
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d2, sdmmc_slot_gpio_sig[slot].d2, GPIO_MODE_INPUT_OUTPUT, "d2", use_gpio_matrix);
+        configure_pin(slot_gpio->d1, sdmmc_slot_gpio_sig[slot].d1, GPIO_MODE_INPUT_OUTPUT, "d1", use_gpio_matrix);
+        configure_pin(slot_gpio->d2, sdmmc_slot_gpio_sig[slot].d2, GPIO_MODE_INPUT_OUTPUT, "d2", use_gpio_matrix);
         // Force D3 high to make slave enter SD mode.
         // Connect to peripheral after width configuration.
-        gpio_config_t gpio_conf = {
-            .pin_bit_mask = BIT64(s_host_ctx.slot_ctx[slot].slot_gpio_num.d3),
-            .mode = GPIO_MODE_OUTPUT,
-            .pull_up_en = 0,
-            .pull_down_en = 0,
-            .intr_type = GPIO_INTR_DISABLE,
-        };
-        gpio_config(&gpio_conf);
-        gpio_set_level(s_host_ctx.slot_ctx[slot].slot_gpio_num.d3, 1);
+        if (slot_gpio->d3 > GPIO_NUM_NC) {
+            gpio_config_t gpio_conf = {
+                .pin_bit_mask = BIT64(slot_gpio->d3),
+                .mode = GPIO_MODE_OUTPUT,
+                .pull_up_en = 0,
+                .pull_down_en = 0,
+                .intr_type = GPIO_INTR_DISABLE,
+            };
+            gpio_config(&gpio_conf);
+            gpio_set_level(slot_gpio->d3, 1);
+        }
     }
     if (slot_width == 8) {
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d4, sdmmc_slot_gpio_sig[slot].d4, GPIO_MODE_INPUT_OUTPUT, "d4", use_gpio_matrix);
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d5, sdmmc_slot_gpio_sig[slot].d5, GPIO_MODE_INPUT_OUTPUT, "d5", use_gpio_matrix);
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d6, sdmmc_slot_gpio_sig[slot].d6, GPIO_MODE_INPUT_OUTPUT, "d6", use_gpio_matrix);
-        configure_pin(s_host_ctx.slot_ctx[slot].slot_gpio_num.d7, sdmmc_slot_gpio_sig[slot].d7, GPIO_MODE_INPUT_OUTPUT, "d7", use_gpio_matrix);
+        configure_pin(slot_gpio->d4, sdmmc_slot_gpio_sig[slot].d4, GPIO_MODE_INPUT_OUTPUT, "d4", use_gpio_matrix);
+        configure_pin(slot_gpio->d5, sdmmc_slot_gpio_sig[slot].d5, GPIO_MODE_INPUT_OUTPUT, "d5", use_gpio_matrix);
+        configure_pin(slot_gpio->d6, sdmmc_slot_gpio_sig[slot].d6, GPIO_MODE_INPUT_OUTPUT, "d6", use_gpio_matrix);
+        configure_pin(slot_gpio->d7, sdmmc_slot_gpio_sig[slot].d7, GPIO_MODE_INPUT_OUTPUT, "d7", use_gpio_matrix);
     }
 
     // SDIO slave interrupt is edge sensitive to ~(int_n | card_int | card_detect)

components/esp_hw_support/include/esp_intr_alloc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -317,6 +317,18 @@ static inline int esp_intr_level_to_flags(int level)
  */
 esp_err_t esp_intr_dump(FILE *stream);
 
+
+/**
+ * @brief Check if the given pointer is in the safe ISR area.
+ * In other words, make sure that the pointer's content is accessible at
+ * any time, regardless of the cache status
+ *
+ * @param ptr Pointer to check
+ *
+ * @return true if `ptr` points to ISR area, false else
+ */
+bool esp_intr_ptr_in_isr_region(void* ptr);
+
 /**@}*/
 
 

components/esp_hw_support/include/esp_memory_utils.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -307,14 +307,37 @@ inline static bool esp_ptr_in_drom(const void *p) {
     /* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is
      * added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB
      * (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000).
-     * The drom_start_addr has to be moved by 0x4000 (16kB) to accomodate
+     * The drom_start_addr has to be moved by 0x4000 (16kB) to accommodate
      * this addition. */
     drom_start_addr += 0x4000;
 #endif
 
     return ((intptr_t)p >= drom_start_addr && (intptr_t)p < SOC_DROM_HIGH);
 }
 
+
+/**
+ * @brief Check if the given pointer is in ROM
+ *
+ * @param ptr Pointer to check
+ *
+ * @return true if `ptr` points to ROM, false else
+ */
+__attribute__((always_inline))
+inline static bool esp_ptr_in_rom(const void *p)
+{
+    intptr_t ip = (intptr_t) p;
+    return
+    /**
+     * The following DROM macros are only defined on RISC-V targets, moreover, to prevent
+     * the compiler from generating a `logical-op` warning, make sure the macros are
+     * distinct. */
+#if CONFIG_IDF_TARGET_ARCH_RISCV && SOC_DROM_MASK_LOW != SOC_IROM_MASK_LOW
+        (ip >= SOC_DROM_MASK_LOW && ip < SOC_DROM_MASK_HIGH) ||
+#endif
+        (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH);
+}
+
 /**
  * @brief Check if the stack pointer is in dram
  *

components/esp_hw_support/intr_alloc.c

@@ -472,6 +472,13 @@ static void IRAM_ATTR non_shared_intr_isr(void *arg)
 }
 #endif
 
+
+bool esp_intr_ptr_in_isr_region(void* ptr)
+{
+    return esp_ptr_in_iram(ptr) || esp_ptr_in_rtc_iram_fast(ptr) || esp_ptr_in_rom(ptr);
+}
+
+
 //We use ESP_EARLY_LOG* here because this can be called before the scheduler is running.
 esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler,
                                     void *arg, intr_handle_t *ret_handle)
@@ -499,7 +506,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
     //ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
     //we need to make sure the interrupt is connected to the CPU0.
     //CPU1 does not have access to the RTC fast memory through this region.
-    if ((flags & ESP_INTR_FLAG_IRAM) && handler && !esp_ptr_in_iram(handler) && !esp_ptr_in_rtc_iram_fast(handler)) {
+    if ((flags & ESP_INTR_FLAG_IRAM) && handler && !esp_intr_ptr_in_isr_region(handler)) {
         return ESP_ERR_INVALID_ARG;
     }
 

components/esp_hw_support/port/esp32p4/esp_clk_tree.c

@@ -51,8 +51,9 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
     case SOC_MOD_CLK_MPLL:
         clk_src_freq = clk_ll_mpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()) * MHZ;
         break;
-    // case SOC_MOD_CLK_APLL: TODO: IDF-8884
-    //     break;
+    case SOC_MOD_CLK_APLL:
+        clk_src_freq = clk_hal_apll_get_freq_hz();
+        break;
     // case SOC_MOD_CLK_SDIO_PLL: TODO: IDF-8886
     //     break;
     case SOC_MOD_CLK_RTC_SLOW: