GitHub - tars3017/Logic-Design-Final-Project

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
final_project.runs/impl_1		final_project.runs/impl_1
pictures		pictures
speaker		speaker
Basys3_Master.xdc		Basys3_Master.xdc
KeyboardCtrl.v		KeyboardCtrl.v
KeyboardDecoder.v		KeyboardDecoder.v
Ps2Interface.v		Ps2Interface.v
README.md		README.md
clock_divisor.v		clock_divisor.v
count_time.v		count_time.v
display.v		display.v
final_project.xpr		final_project.xpr
fsm.v		fsm.v
lfsr.v		lfsr.v
maps.v		maps.v
mem_addr_gen.v		mem_addr_gen.v
scan_ctl.v		scan_ctl.v
stopwatch.v		stopwatch.v
top.v		top.v
trophy_control.v		trophy_control.v
vga.v		vga.v

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