Add zcu102 platform support.

.gitignore

@@ -24,4 +24,7 @@ Image*
 *.ext4
 *.qcow2
 *.dtb
-.DS_Store
+.DS_Store
+temp-fit.its
+fitImage
+sd.img

.vscode/settings.json

@@ -76,7 +76,7 @@
 	// "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
 	// "rust-analyzer.cargo.target": "loongarch64-unknown-none",
 	"rust-analyzer.checkOnSave.allTargets": false,
-	// "rust-analyzer.cargo.features": [
-	//     "board_qemu"
-	// ]
+	"rust-analyzer.cargo.features": [
+	    "platform_zcu102"
+	]
 }

Cargo.toml

@@ -32,6 +32,9 @@ loongArch64 = "0.2.4"
 [features]
 platform_qemu = []
 platform_imx8mp = []
+platform_zcu102 = []
+gicv3 = []
+gicv2 = []
 
 [profile.dev]
 panic = "abort"

Makefile

@@ -6,7 +6,8 @@ PORT ?= 2333
 MODE ?= debug
 OBJCOPY ?= rust-objcopy --binary-architecture=$(ARCH)
 KDIR ?= ../../linux
-FEATURES ?= platform_qemu
+FEATURES ?= platform_zcu102,gicv2
+BOARD ?= zcu102
 
 ifeq ($(ARCH),aarch64)
     RUSTC_TARGET := aarch64-unknown-none
@@ -38,7 +39,6 @@ build_args += --target $(RUSTC_TARGET)
 build_args += -Z build-std=core,alloc
 build_args += -Z build-std-features=compiler-builtins-mem
 
-
 ifeq ($(MODE), release)
   build_args += --release
 endif
@@ -78,8 +78,6 @@ cp: all
 clean:
 	cargo clean
 
-ifeq ($(ARCH),loongarch64)
-include scripts/3a5000-loongarch64.mk
-else
-include scripts/qemu-$(ARCH).mk
-endif
+# set the BOARD variable to "3a5000"/qemu/zcu102/imx8mp to
+# include the corresponding script under the ./scripts directory
+include scripts/${BOARD}-${ARCH}.mk

images/aarch64/devicetree/linux1-v2.dts

@@ -0,0 +1,97 @@
+/dts-v1/;
+
+/ {
+	#size-cells = <0x02>;
+	#address-cells = <0x02>;
+	interrupt-parent = <0x01>;
+	model = "linux,dummy-virt";
+	compatible = "linux,dummy-virt";
+
+	cpus {
+		#size-cells = <0x00>;
+		#address-cells = <0x01>;
+
+		cpu@0 {
+			phandle = <0x8010>;
+			reg = <0x00>;
+			enable-method = "psci";
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+		};
+
+		cpu@1 {
+			phandle = <0x800f>;
+			reg = <0x01>;
+			enable-method = "psci";
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory@50000000 {
+		device_type = "memory";
+		reg = <0x00 0x50000000 0x00 0x80000000>;
+	};
+
+	intc@8000000 {
+		phandle = <0x01>;
+		interrupts = <0x01 0x09 0x04>;
+		reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000 0x00 0x8030000 0x00 0x10000 0x00 0x8040000 0x00 0x10000>;
+		compatible = "arm,cortex-a15-gic";
+		ranges;
+		#size-cells = <0x02>;
+		#address-cells = <0x02>;
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+	};
+
+	apb-pclk {
+		phandle = <0x8000>;
+		clock-output-names = "clk24mhz";
+		clock-frequency = <0x16e3600>;
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+	};
+
+	pl011@9000000 {
+		clock-names = "uartclk\0apb_pclk";
+		clocks = <0x8000 0x8000>;
+		interrupt-parent = <0x01>;
+		interrupts = <0x00 0x01 0x04>;
+		reg = <0x00 0x9000000 0x00 0x1000>;
+		compatible = "arm,pl011\0arm,primecell";
+	};
+
+	timer {
+		interrupt-parent = <0x01>;
+		interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
+		always-on;
+		compatible = "arm,armv8-timer\0arm,armv7-timer";
+	};
+
+	virtio_mmio@a003a00 {
+		dma-coherent;
+		interrupt-parent = <0x01>;
+		interrupts = <0x00 0x2d 0x01>;
+		reg = <0x00 0xa003a00 0x00 0x200>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@a003e00 {
+		dma-coherent;
+		interrupt-parent = <0x01>;
+		interrupts = <0x00 0x2f 0x01>;
+		reg = <0x00 0xa003e00 0x00 0x200>;
+		compatible = "virtio,mmio";
+	};
+
+	chosen {
+		bootargs = "earlycon console=ttyAMA0 root=/dev/vda mem=768M rw";
+		stdout-path = "/pl011@9000000";
+	};
+};

images/aarch64/devicetree/linux1.dts

@@ -194,10 +194,4 @@
 		interrupt-parent = <0x01>;
 		interrupts = <0x00 0x20 0x01>;
 	};
-
-	hvisor_ivc_device {
-        compatible = "hvisor";
-        interrupt-parent = <0x01>;
-        interrupts = <0x00 0x21 0x01>;
-    };
 };

images/aarch64/devicetree/zcu102-nonroot-aarch64.dts

@@ -0,0 +1,126 @@
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,zynqmp-zcu102-revB\0xlnx,zynqmp-zcu102\0xlnx,zynqmp";
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	model = "ZynqMP ZCU102 RevB";
+
+    cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x02>;
+			operating-points-v2 = <0x01>;
+			cpu-idle-states = <0x02>;
+			next-level-cache = <0x03>;
+			phandle = <0x08>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x03>;
+			operating-points-v2 = <0x01>;
+			cpu-idle-states = <0x02>;
+			next-level-cache = <0x03>;
+			phandle = <0x09>;
+		};
+
+		l2-cache {
+			compatible = "cache";
+			cache-level = <0x02>;
+			phandle = <0x03>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x40000000>;
+				local-timer-stop;
+				entry-latency-us = <0x12c>;
+				exit-latency-us = <0x258>;
+				min-residency-us = <0x2710>;
+				phandle = <0x02>;
+			};
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <0x05>;
+		interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>;
+		interrupt-affinity = <0x06 0x07 0x08 0x09>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+    memory@0 {
+		device_type = "memory";
+		reg = <0x00 0x50000000 0x00 0x25000000>;
+	};
+
+    timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <0x05>;
+		interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
+	};
+
+    axi {
+		compatible = "simple-bus";
+		bootph-all;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		phandle = <0x58>;
+
+		interrupt-controller@f9010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <0x03>;
+			reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>;
+			interrupt-controller;
+			interrupt-parent = <0x05>;
+			interrupts = <0x01 0x09 0xf04>;
+			num_cpus = <0x02>;
+			num_interrupts = <0x60>;
+			phandle = <0x05>;
+		};
+    };
+
+
+    aliases {
+	};
+
+	// virtio blk
+	virtio_mmio@ff9d0000 {
+		dma-coherent;
+		interrupt-parent = <0x05>;
+		interrupts = <0x0 0x2e 0x1>;
+		reg = <0x0 0xff9d0000 0x0 0x200>;
+		compatible = "virtio,mmio";
+	};
+
+	// virtio serial
+	virtio_mmio@ff9e0000 {
+		dma-coherent;
+		interrupt-parent = <0x05>;
+		interrupts = <0x0 0x2c 0x1>;
+		reg = <0x0 0xff9e0000 0x0 0x200>;
+		compatible = "virtio,mmio";
+	};
+
+    chosen {
+		bootargs = "earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw";
+		stdout-path = "/virtio_mmio@0xff9e0000";
+	};
+};