Chip Design and System Group (CDSG)
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Sun Yat-sen University
- Guangzhou, China
Pinned Loading
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DeepRL-Scheduling
DeepRL-Scheduling PublicA Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
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Graph-Processing-System
Graph-Processing-System PublicA Compiler and Runtime System for Concurrent Graph Processing
C++
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HLS-System
HLS-System PublicEntropy-Directed Scheduling in High-Level Synthesis for FPGA Chips
C++ 2
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