I2C failed due to wrong check condition

[fpistm]

When introducing HALv2, some binary variables have been changed from uint8_t to bool.
A mistake was introduce in the HAL_I2C_ErrorCallback function.

-  if (obj->isMaster == 0) {
+  if (obj->isMaster) {
+#if defined(USE_HALV2_DRIVER)
+    HAL_I2C_SLAVE_EnableListen_IT(hi2c);
+#else
     HAL_I2C_EnableListen_IT(hi2c);
+#endif

New condition was wrong as it should be:
if (!obj->isMaster)

[electrical-pro]

@fpistm Thanks for this fix — confirmed the root cause is real, caught I2C1->CR1 == 0x8000 (only SWRST set) on an F103C6 slave during a live failure, matches this bug exactly.

One thing though: this fix doesn't actually recover from a BERR specifically. In stm32f1xx_hal_i2c.c, I2C_ITError() only resets hi2c->State to READY for AF+LISTEN — not for BERR (which is the case that also sets SWRST). Since HAL_I2C_EnableListen_IT() requires State == READY to do anything, calling it after a BERR is a silent no-op. Tested it — same behavior before and after this patch for that specific case.

Here's how I trigger a BERR on demand for testing, from the master side (ESP32, bit-banging instead of using Wire):

  pinMode(SDA, OUTPUT_OPEN_DRAIN);
  pinMode(SCL, OUTPUT_OPEN_DRAIN);

  digitalWrite(SDA, HIGH);
  digitalWrite(SCL, HIGH);
  delayMicroseconds(5);

  // START condition
  digitalWrite(SDA, LOW);
  delayMicroseconds(5);
  digitalWrite(SCL, LOW);
  delayMicroseconds(5);

  // clock out only 4 of 8 address bits — incomplete on purpose
  uint8_t addr = (SLAVE_ADDR << 1);
  for (int i = 0; i < 4; i++) {
    digitalWrite(SDA, (addr & 0x80) ? HIGH : LOW);
    addr <<= 1;
    delayMicroseconds(5);
    digitalWrite(SCL, HIGH);
    delayMicroseconds(5);
    digitalWrite(SCL, LOW);
    delayMicroseconds(5);
  }

  // misplaced STOP: SDA rises while SCL is HIGH, mid-byte -> BERR
  digitalWrite(SDA, LOW);
  delayMicroseconds(5);
  digitalWrite(SCL, HIGH);
  delayMicroseconds(5);
  digitalWrite(SDA, HIGH);
  delayMicroseconds(5);

After running this, the slave just NACKs — clean Wire.endTransmission() == 2 style, not a timeout. Confirmed it's actually a BERR by checking I2C1->CR1 on the STM32 side afterward — reads 0x8000 (only SWRST set).