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Add regression test for synthesisable for loop check (issue #687)
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martinwhitaker committed Jan 7, 2024
1 parent 974d2b8 commit fa2dfe6
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10 changes: 10 additions & 0 deletions ivtest/gold/br_gh687-vvp-stdout.gold
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25 changes: 25 additions & 0 deletions ivtest/ivltests/br_gh687.v
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module top;
logic [9:0] pipe = 0;
logic [4:0] i;
logic clk = 0;

always #1 clk = ~clk;

always_ff @(posedge clk) begin
for (i=0; i<9; i++) begin
pipe[i+1] <= pipe[i];
end
pipe[0] <= pipe[9];
end

initial begin
pipe[0] = 1'b1;

for (int j=0; j<10; j++) begin
$display(pipe[9]);
#2;
end

$finish(0);
end
endmodule
1 change: 1 addition & 0 deletions ivtest/regress-vvp.list
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Expand Up @@ -23,6 +23,7 @@ br_gh383b vvp_tests/br_gh383b.json
br_gh383c vvp_tests/br_gh383c.json
br_gh383d vvp_tests/br_gh383d.json
br_gh440 vvp_tests/br_gh440.json
br_gh687 vvp_tests/br_gh687.json
br_gh939 vvp_tests/br_gh939.json
br_gh1018 vvp_tests/br_gh1018.json
br_gh1029 vvp_tests/br_gh1029.json
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6 changes: 6 additions & 0 deletions ivtest/vvp_tests/br_gh687.json
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{
"type" : "normal",
"source" : "br_gh687.v",
"gold" : "br_gh687",
"iverilog-args" : [ "-g2009" ]
}

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