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Add regression tests for early signal elaboration.
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martinwhitaker committed Apr 6, 2024
1 parent ca30705 commit ef7f0a8
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2 changes: 2 additions & 0 deletions ivtest/gold/early_sig_elab3-iverilog-stderr.gold
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ivltests/early_sig_elab3.v:8: error: Circular dependency detected in declaration of 'a'.
1 error(s) during elaboration.
18 changes: 18 additions & 0 deletions ivtest/ivltests/br_gh1097.v
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module test_mod ();

typedef enum logic [4:0] {ENUM_ELEM1, ENUM_ELEM2} test_enum_t;

test_enum_t test_mem_addr_e;
logic [1:0] test_mem [test_mem_addr_e.num()];

initial begin
test_mem[ENUM_ELEM1] = 1;
test_mem[ENUM_ELEM2] = 2;
$display("ENUM_ELEM1 = %d test_mem[ENUM_ELEM1] = %d", ENUM_ELEM1, test_mem[ENUM_ELEM1]);
$display("ENUM_ELEM2 = %d test_mem[ENUM_ELEM2] = %d", ENUM_ELEM2, test_mem[ENUM_ELEM2]);
if (test_mem[ENUM_ELEM1] === 1 && test_mem[ENUM_ELEM2] === 2)
$display("PASSED");
else
$display("FAILED");
end
endmodule
21 changes: 21 additions & 0 deletions ivtest/ivltests/br_gh483a.v
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// Strictly speaking this is illegal as it uses a hierarchical name in a
// constant expression.
module top;
parameter ENABLE = 1;
if (ENABLE) begin : blk
wire [7:0] w;
end
wire [7:0] x;
wire [$bits(blk.w)-1:0] y = 8'h55;
wire [$bits(x)-1:0] z = 8'haa;
initial begin
$display("blk.w: %b (%0d bits)", blk.w, $bits(blk.w));
$display("x: %b (%0d bits)", x, $bits(x));
$display("y: %b (%0d bits)", y, $bits(y));
$display("z: %b (%0d bits)", z, $bits(z));
if (y === 8'h55 && z === 8'haa)
$display("PASSED");
else
$display("FAILED");
end
endmodule
18 changes: 18 additions & 0 deletions ivtest/ivltests/br_gh483b.v
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module Module;
parameter T = 10;
wire [T-1:0] x = 8'h55;
initial $display("Module %b %0d", x, T);
endmodule

module top;
wire [7:0] x;
Module #($bits(x)) mA();
Module #(8) mB();

initial begin
if (mA.x === 8'h55 && mB.x === 8'h55)
$display("PASSED");
else
$display("FAILED");
end
endmodule
25 changes: 25 additions & 0 deletions ivtest/ivltests/early_sig_elab1.v
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// Icarus elaborates signals in alphabetical order, so force early
// elaboration that way.

module test;

localparam LSB = 0;
localparam MSB = 7;

reg [MSB:LSB] c;
reg [$bits(c):1] a;

localparam WIDTH = $bits(c);

reg [WIDTH:1] b;

initial begin
$display("a = %b", a);
$display("b = %b", b);
if ($bits(a) === 8 && $bits(b) == 8)
$display("PASSED");
else
$display("FAILED");
end

endmodule
27 changes: 27 additions & 0 deletions ivtest/ivltests/early_sig_elab2.v
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// Strictly speaking this is not legal as it uses a hierarchical name in a
// constant expression,

module test1;

reg [$bits(test2.v):1] v;

endmodule

module test2;

reg [7:0] v;

initial begin
if ($bits(test1.v) === 8 && $bits(test3.v) === 8)
$display("PASSED");
else
$display("FAILED");
end

endmodule

module test3;

reg [$bits(test2.v):1] v;

endmodule
16 changes: 16 additions & 0 deletions ivtest/ivltests/early_sig_elab3.v
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// Test we detect and report circular dependencies.

// Strictly speaking this is not legal as it uses a hierarchical name in a
// constant expression,

module test;

reg [$bits(test.b):1] a;
reg [$bits(test.a):1] b;

initial begin
// This test is expected to fail at compile time.
$display("FAILED");
end

endmodule
6 changes: 6 additions & 0 deletions ivtest/regress-vvp.list
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Expand Up @@ -25,6 +25,8 @@ br_gh383b vvp_tests/br_gh383b.json
br_gh383c vvp_tests/br_gh383c.json
br_gh383d vvp_tests/br_gh383d.json
br_gh440 vvp_tests/br_gh440.json
br_gh483a vvp_tests/br_gh483a.json
br_gh483b vvp_tests/br_gh483b.json
br_gh552 vvp_tests/br_gh552.json
br_gh687 vvp_tests/br_gh687.json
br_gh703 vvp_tests/br_gh703.json
Expand All @@ -42,6 +44,7 @@ br_gh1087a2 vvp_tests/br_gh1087a2.json
br_gh1087a3 vvp_tests/br_gh1087a3.json
br_gh1087b vvp_tests/br_gh1087b.json
br_gh1087c vvp_tests/br_gh1087c.json
br_gh1097 vvp_tests/br_gh1097.json
br_gh1099a vvp_tests/br_gh1099a.json
br_gh1099b vvp_tests/br_gh1099b.json
br_gh1099c vvp_tests/br_gh1099c.json
Expand Down Expand Up @@ -84,6 +87,9 @@ dffsynth9 vvp_tests/dffsynth9.json
dffsynth10 vvp_tests/dffsynth10.json
dffsynth11 vvp_tests/dffsynth11.json
dumpfile vvp_tests/dumpfile.json
early_sig_elab1 vvp_tests/early_sig_elab1.json
early_sig_elab2 vvp_tests/early_sig_elab2.json
early_sig_elab3 vvp_tests/early_sig_elab3.json
eofmt_percent vvp_tests/eofmt_percent.json
eofmt_percent-vlog95 vvp_tests/eofmt_percent-vlog95.json
fdisplay3 vvp_tests/fdisplay3.json
Expand Down
5 changes: 5 additions & 0 deletions ivtest/vvp_tests/br_gh1097.json
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{
"type" : "normal",
"source" : "br_gh1097.v",
"iverilog-args" : [ "-g2009" ]
}
4 changes: 4 additions & 0 deletions ivtest/vvp_tests/br_gh483a.json
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{
"type" : "normal",
"source" : "br_gh483a.v"
}
4 changes: 4 additions & 0 deletions ivtest/vvp_tests/br_gh483b.json
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{
"type" : "normal",
"source" : "br_gh483b.v"
}
4 changes: 4 additions & 0 deletions ivtest/vvp_tests/early_sig_elab1.json
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{
"type" : "normal",
"source" : "early_sig_elab1.v"
}
4 changes: 4 additions & 0 deletions ivtest/vvp_tests/early_sig_elab2.json
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{
"type" : "normal",
"source" : "early_sig_elab2.v"
}
5 changes: 5 additions & 0 deletions ivtest/vvp_tests/early_sig_elab3.json
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{
"type" : "CE",
"source" : "early_sig_elab3.v",
"gold" : "early_sig_elab3"
}

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