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ivtest: Add regression test to check that shift rhs is always unsigned
Add a regression test to check that the right-hand side of a shift operation is always treated as unsigned, even if it is a signed registers or a variation thereof. Signed-off-by: Lars-Peter Clausen <[email protected]>
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module test; | ||
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// Check that the right hand side for a shift instruction is always treated as | ||
// unsigned. Even if its a signed register, or a transformation thereof. | ||
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reg failed = 1'b0; | ||
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`define check(val, exp) \ | ||
if ((val) !== (exp)) begin \ | ||
$display("FAILED(%0d): `%s`, expected `%0d`, got `%0d`.", `__LINE__, \ | ||
`"val`", (exp), (val), 4); \ | ||
failed = 1'b1; \ | ||
end | ||
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reg signed [1:0] shift = 2'b10; | ||
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initial begin | ||
`check(1 << shift, 4) | ||
`check(1 << shift[1:0], 4) | ||
`check(2 << shift[1], 4) | ||
`check(1 << $unsigned(shift), 4) | ||
`check(1 << $signed(shift), 4) | ||
`check(1 << {shift}, 4) | ||
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`check(1 <<< shift, 4) | ||
`check(1 <<< shift[1:0], 4) | ||
`check(2 <<< shift[1], 4) | ||
`check(1 <<< $unsigned(shift), 4) | ||
`check(1 <<< $signed(shift), 4) | ||
`check(1 <<< {shift}, 4) | ||
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`check(16 >> shift, 4) | ||
`check(16 >> shift[1:0], 4) | ||
`check(8 >> shift[1], 4) | ||
`check(16 >> $unsigned(shift), 4) | ||
`check(16 >> $signed(shift), 4) | ||
`check(16 >> {shift}, 4) | ||
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`check(16 >>> shift, 4) | ||
`check(16 >>> shift[1:0], 4) | ||
`check(8 >>> shift[1], 4) | ||
`check(16 >>> $unsigned(shift), 4) | ||
`check(16 >>> $signed(shift), 4) | ||
`check(16 >>> {shift}, 4) | ||
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if (!failed) begin | ||
$display("PASSED"); | ||
end | ||
end | ||
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endmodule |
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{ | ||
"type" : "normal", | ||
"source" : "shift6.v" | ||
} |