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ivtest: Add regression test for undefined intra-assignment delay
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Check that assignments with undefined intra-assignment delay get executed
with zero delay. The assignment should not be skipped.

Signed-off-by: Lars-Peter Clausen <[email protected]>
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larsclausen committed Sep 2, 2024
1 parent 80fd301 commit 1ac2020
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53 changes: 53 additions & 0 deletions ivtest/ivltests/vardly_undefined_vec.v
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module test;
// Test that delay values of 'z and 'x get treated as a zero delay. Check this
// for different types of assignments. The assignment should not be skipped.

reg failed = 1'b0;

`define check(expr, val) \
if (expr !== val) begin \
$display("FAILED(%0d): `%s`, expected %0x, got %0x", `__LINE__, `"expr`", val, expr); \
failed = 1'b1; \
end


integer delay_x = 32'hx;
wire [31:0] delay_z;

reg [31:0] x;
reg [31:0] a[0:1];
integer i = 0, j = 0;

`define test(var) \
// Non-blocking \
var = 0; \
var <= #delay_x 1; \
#1 `check(var, 1) \
var = 0; \
var <= #delay_z 1; \
#1 `check(var, 1) \
// blocking \
var = 0; \
var = #delay_x 1; \
`check(var, 1) \
var = 0; \
var = #delay_z 1; \
`check(var, 1)

initial begin
`test(x)
`test(x[0])
`test(x[i])
`test(a[0])
`test(a[0][0])
`test(a[0][j])
`test(a[i])
`test(a[i][0])
`test(a[i][j])

if (!failed) begin
$display("PASSED");
end
end

endmodule
1 change: 1 addition & 0 deletions ivtest/regress-vvp.list
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Expand Up @@ -266,6 +266,7 @@ vams_abs2 vvp_tests/vams_abs2.json
vams_abs2-vlog95 vvp_tests/vams_abs2-vlog95.json
vams_abs3 vvp_tests/vams_abs3.json
vams_abs3-vlog95 vvp_tests/vams_abs3-vlog95.json
vardly_undefined_vec vvp_tests/vardly_undefined_vec.json
va_math vvp_tests/va_math.json
warn_opt_sys_tf vvp_tests/warn_opt_sys_tf.json
wreal vvp_tests/wreal.json
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4 changes: 4 additions & 0 deletions ivtest/vvp_tests/vardly_undefined_vec.json
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{
"type" : "normal",
"source" : "vardly_undefined_vec.v"
}

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