Skip to content

Commit

Permalink
Refactored IO naming to explicit IN and OUT in settings module
Browse files Browse the repository at this point in the history
  • Loading branch information
@skuep
skuep committed Sep 18, 2024
1 parent 595e790 commit 97f82cf
Show file tree
Hide file tree
Showing 5 changed files with 83 additions and 83 deletions.
32 changes: 16 additions & 16 deletions stm32/aioc-fw/Src/io.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,71 +8,71 @@ void IO_IN_EXTI_ISR(void)
if (EXTI->PR & IO_IN_PIN_1_EXTI_PR) {
uint8_t state = IO_IN_GPIO->IDR & IO_IN_PIN_1 ? 0x00 : 0x01;

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX0] & SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX0] & SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLUP : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX1] & SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX1] & SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN1_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLDN : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX2] & SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX2] & SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN1_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_PLAYMUTE : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX3] & SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX3] & SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN1_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_RECMUTE : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX0] & SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX0] & SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DCD : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX1] & SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX1] & SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN1_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DSR : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX2] & SETTINGS_REG_SERIAL_IOMUX2_RISRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX2] & SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN1_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_RI : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX3] & SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IO1_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX3] & SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN1_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_BREAK : 0x00);
}
}

if (EXTI->PR & IO_IN_PIN_2_EXTI_PR) {
uint8_t state = IO_IN_GPIO->IDR & IO_IN_PIN_2 ? 0x00 : 0x01;

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX0] & SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX0] & SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLUP : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX1] & SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX1] & SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN2_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLDN : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX2] & SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX2] & SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN2_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_PLAYMUTE : 0x00);
}

if (settingsRegMap[SETTINGS_REG_CM108_IOMUX3] & SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_CM108_IOMUX3] & SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN2_MASK) {
USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_RECMUTE : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX0] & SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX0] & SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DCD : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX1] & SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX1] & SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN2_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DSR : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX2] & SETTINGS_REG_SERIAL_IOMUX2_RISRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX2] & SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN2_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_RI : 0x00);
}

if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX3] & SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IO2_MASK) {
if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX3] & SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN2_MASK) {
USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_BREAK : 0x00);
}
}
Expand Down
94 changes: 47 additions & 47 deletions stm32/aioc-fw/Src/settings.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,50 +30,50 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];

/* AIOC IOMUX0 register */
#define SETTINGS_REG_AIOC_IOMUX0 0x24
#define SETTINGS_REG_AIOC_IOMUX0_DEFAULT (SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_DFLT)
/* PTT1SRC: Source for PTT1 signal */
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_DFLT (SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO3_MASK | SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTRNRTS_MASK)
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_OFFS 0
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_MASK 0xFFFFFFFFUL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_NONE_MASK 0x00000000UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO1_MASK 0x00000001UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO2_MASK 0x00000002UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO3_MASK 0x00000004UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO4_MASK 0x00000008UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTR_MASK 0x00000100UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALRTS_MASK 0x00000200UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTRNRTS_MASK 0x00000400UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALNDTRRTS_MASK 0x00000800UL
#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK 0x00001000UL
#define SETTINGS_REG_AIOC_IOMUX0_DEFAULT (SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_DFLT)
/* OUT1SRC: Source for OUT1 signal */
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_DFLT (SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK | SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK)
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_OFFS 0
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_MASK 0xFFFFFFFFUL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_NONE_MASK 0x00000000UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO1_MASK 0x00000001UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO2_MASK 0x00000002UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK 0x00000004UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO4_MASK 0x00000008UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTR_MASK 0x00000100UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALRTS_MASK 0x00000200UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK 0x00000400UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALNDTRRTS_MASK 0x00000800UL
#define SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK 0x00001000UL

/* AIOC IOMUX1 register */
#define SETTINGS_REG_AIOC_IOMUX1 0x25
#define SETTINGS_REG_AIOC_IOMUX1_DEFAULT (SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_DFLT)
/* PTT2SRC: Source for PTT2 signal */
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_DFLT (SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_CM108GPIO4_MASK)
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_OFFS SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_OFFS
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_NONE_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_NONE_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_CM108GPIO1_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO1_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_CM108GPIO2_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO2_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_CM108GPIO3_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO3_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_CM108GPIO4_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_CM108GPIO4_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALDTR_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTR_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALDTRNRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTRNRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALNDTRRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALNDTRRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_VPTT_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK
#define SETTINGS_REG_AIOC_IOMUX1_DEFAULT (SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_DFLT)
/* OUT2SRC: Source for OUT2 signal */
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_DFLT (SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO4_MASK)
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_OFFS SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_OFFS
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_NONE_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_NONE_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO1_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO1_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO2_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO2_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO3_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO3_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_CM108GPIO4_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_CM108GPIO4_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALDTR_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTR_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALDTRNRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALDTRNRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_SERIALNDTRRTS_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_SERIALNDTRRTS_MASK
#define SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_VPTT_MASK SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK

/* CM108 IOMUX0 register */
#define SETTINGS_REG_CM108_IOMUX0 0x44
#define SETTINGS_REG_CM108_IOMUX0_DEFAULT (SETTINGS_REG_CM108_IOMUX0_BTN1SRC_DFLT)
/* BTN1SRC: Volume-Up Button source */
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_DFLT (SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK)
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_DFLT (SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK)
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS 0
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK 0xFFFFFFFFUL
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK 0x00000000UL
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK 0x00010000UL /* AIOC's IO1 */
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK 0x00020000UL /* AIOC's IO2 */
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK 0x00010000UL /* AIOC's IN1 */
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK 0x00020000UL /* AIOC's IN2 */
#define SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK 0x01000000UL /* Virtual COS */

/* CM108 IOMUX1 register */
Expand All @@ -84,8 +84,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IO1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IO2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
#define SETTINGS_REG_CM108_IOMUX1_BTN2SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK

/* CM108 IOMUX2 register */
Expand All @@ -96,8 +96,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IO1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IO2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
#define SETTINGS_REG_CM108_IOMUX2_BTN3SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK

/* CM108 IOMUX3 register */
Expand All @@ -108,8 +108,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IO1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IO2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK

/* Serial (CDC) Control register */
Expand Down Expand Up @@ -138,8 +138,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS SETTINGS_REG_CM108_IOMUX0_BTN1SRC_OFFS
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_NONE_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO1_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IO2_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN1_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_IN2_MASK
#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK

/* Serial (CDC) IOMUX1 register */
Expand All @@ -150,8 +150,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IO1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO1_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IO2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO2_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK

/* Serial (CDC) IOMUX2 register */
Expand All @@ -162,8 +162,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IO1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO1_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IO2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO2_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK

/* Serial (CDC) IOMUX3 register */
Expand All @@ -174,8 +174,8 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_OFFS SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_OFFS
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_NONE_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_NONE_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IO1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO1_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IO2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IO2_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN1_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN1_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_IN2_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_IN2_MASK
#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK

/* Virtual PTT level control register */
Expand Down
8 changes: 4 additions & 4 deletions stm32/aioc-fw/Src/usb_audio.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -776,8 +776,8 @@ void TIM16_IRQHandler(void)

/* Assert enabled PTTs */
uint8_t pttMask = IO_PTT_MASK_NONE;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX0] & SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK ? IO_PTT_MASK_PTT1 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX1] & SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_VPTT_MASK ? IO_PTT_MASK_PTT2 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX0] & SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK ? IO_PTT_MASK_PTT1 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX1] & SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_VPTT_MASK ? IO_PTT_MASK_PTT2 : 0;

IO_PTTAssert(pttMask);
}
Expand All @@ -790,8 +790,8 @@ void TIM16_IRQHandler(void)

/* Deassert enabled PTTs */
uint8_t pttMask = IO_PTT_MASK_NONE;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX0] & SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK ? IO_PTT_MASK_PTT1 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX1] & SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_VPTT_MASK ? IO_PTT_MASK_PTT2 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX0] & SETTINGS_REG_AIOC_IOMUX0_OUT1SRC_VPTT_MASK ? IO_PTT_MASK_PTT1 : 0;
pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX1] & SETTINGS_REG_AIOC_IOMUX1_OUT2SRC_VPTT_MASK ? IO_PTT_MASK_PTT2 : 0;

IO_PTTDeassert(pttMask);
}
Expand Down
Loading

0 comments on commit 97f82cf

Please sign in to comment.