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Added various read-only debug registers to register map
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@skuep
skuep committed Jan 1, 2024
1 parent e853047 commit 2fd3f70
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Showing 2 changed files with 166 additions and 8 deletions.
34 changes: 31 additions & 3 deletions stm32/aioc-fw/Src/settings.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,15 +15,17 @@ void Settings_Init()

uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize)
{
if (address < SETTINGS_REGMAP_SIZE) {
if (address < SETTINGS_REGMAP_READONLYADDR) {
assert(bufsize == sizeof(uint32_t));

uint32_t data = ( (((uint32_t) buffer[0]) << 0) |
(((uint32_t) buffer[1]) << 8) |
(((uint32_t) buffer[2]) << 16) |
(((uint32_t) buffer[3]) << 24) );

__disable_irq();
settingsRegMap[address] = data;
__enable_irq();

return bufsize;
}
Expand All @@ -36,7 +38,9 @@ uint8_t Settings_RegRead(uint8_t address, uint8_t * buffer, uint8_t bufsize)
if (address < SETTINGS_REGMAP_SIZE) {
assert(bufsize == sizeof(uint32_t));

__disable_irq();
uint64_t data = settingsRegMap[address];
__enable_irq();

buffer[0] = (uint8_t) (data >> 0);
buffer[1] = (uint8_t) (data >> 8);
Expand All @@ -52,9 +56,12 @@ void Settings_Store(void)
HAL_FLASH_Unlock();

uint32_t pageError = 0;
extern uint32_t * _eeprom;
uint32_t pageAddress = (uint32_t) &_eeprom;

FLASH_EraseInitTypeDef eraseInitStruct = {
.TypeErase = FLASH_TYPEERASE_PAGES,
.PageAddress = SETTINGS_FLASH_ADDRESS,
.PageAddress = pageAddress,
.NbPages = (SETTINGS_REGMAP_SIZE * sizeof(uint32_t) + FLASH_PAGE_SIZE-1) / FLASH_PAGE_SIZE
};

Expand All @@ -64,7 +71,8 @@ void Settings_Store(void)
return;
}

uint32_t wordAddress = SETTINGS_FLASH_ADDRESS;
extern uint32_t * _eeprom;
uint32_t wordAddress = (uint32_t) &_eeprom;
uint32_t wordCount = SETTINGS_REGMAP_SIZE;
uint32_t * wordPtr = settingsRegMap;

Expand Down Expand Up @@ -134,5 +142,25 @@ void Settings_Default(void)
settingsRegMap[SETTINGS_REG_VCOS_LVLCTRL] = SETTINGS_REG_VCOS_LVLCTRL_DEFAULT;
settingsRegMap[SETTINGS_REG_VCOS_TIMCTRL] = SETTINGS_REG_VCOS_TIMCTRL_DEFAULT;

/* AIOC Debug registers */
settingsRegMap[SETTINGS_REG_DBGAIOC0] = SETTINGS_REG_DBGAIOC0_DEFAULT;

/* Audio Debug registers */
settingsRegMap[SETTINGS_REG_DBGAUDIO0] = SETTINGS_REG_DBGAUDIO0_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO1] = SETTINGS_REG_DBGAUDIO1_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO2] = SETTINGS_REG_DBGAUDIO2_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO3] = SETTINGS_REG_DBGAUDIO3_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO4] = SETTINGS_REG_DBGAUDIO4_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO5] = SETTINGS_REG_DBGAUDIO5_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO6] = SETTINGS_REG_DBGAUDIO6_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO7] = SETTINGS_REG_DBGAUDIO7_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO8] = SETTINGS_REG_DBGAUDIO9_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO9] = SETTINGS_REG_DBGAUDIO10_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO10] = SETTINGS_REG_DBGAUDIO11_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO11] = SETTINGS_REG_DBGAUDIO11_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO12] = SETTINGS_REG_DBGAUDIO12_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO13] = SETTINGS_REG_DBGAUDIO13_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO14] = SETTINGS_REG_DBGAUDIO14_DEFAULT;
settingsRegMap[SETTINGS_REG_DBGAUDIO15] = SETTINGS_REG_DBGAUDIO15_DEFAULT;

}
140 changes: 135 additions & 5 deletions stm32/aioc-fw/Src/settings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
#include "usb_descriptors.h"

#define SETTINGS_REGMAP_SIZE 256
#define SETTINGS_REGMAP_READONLYADDR 0xC0

extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];

Expand Down Expand Up @@ -188,10 +189,10 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
/* Virtual PTT timing control register */
#define SETTINGS_REG_VPTT_TIMCTRL 0x84
#define SETTINGS_REG_VPTT_TIMCTRL_DEFAULT (SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT)
/* TIMEOUT: Timeout (trailing) time in microseconds */
#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT ((uint32_t) 10000 << SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS)
/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (20 << 4) << SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS)
#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS 0
#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL
#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK 0xFFFFFFFFUL

/* Virtual COS level control register */
#define SETTINGS_REG_VCOS_LVLCTRL 0x92
Expand All @@ -204,11 +205,140 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
/* Virtual COS timing control register */
#define SETTINGS_REG_VCOS_TIMCTRL 0x94
#define SETTINGS_REG_VCOS_TIMCTRL_DEFAULT (SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT)
/* TIMEOUT: Timeout (trailing) time in microseconds */
#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT ((uint32_t) 10000 << SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS)
/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (200 << 4) << SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS)
#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS 0
#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL

/* AIOC debug register 0 */
#define SETTINGS_REG_DBGAIOC0 0xC0
#define SETTINGS_REG_DBGAIOC0_DEFAULT 0
/* Various digital signal states */
#define SETTINGS_REG_DBGAIOC0_PTT1STATE_MASK 0x00010000UL
#define SETTINGS_REG_DBGAIOC0_PTT2STATE_MASK 0x00020000UL

/* UAC audio debug register 0 */
#define SETTINGS_REG_DBGAUDIO0 0xD0
#define SETTINGS_REG_DBGAUDIO0_DEFAULT 0
/* Playback or recording muted (master and first channel) */
#define SETTINGS_REG_DBGAUDIO0_RECMUTE0_MASK 0x00010000UL
#define SETTINGS_REG_DBGAUDIO0_RECMUTE1_MASK 0x00020000UL
#define SETTINGS_REG_DBGAUDIO0_PLAYMUTE0_MASK 0x00100000UL
#define SETTINGS_REG_DBGAUDIO0_PLAYMUTE1_MASK 0x00200000UL
/* Virtual PTT and COS states */
#define SETTINGS_REG_DBGAIOC0_VPTTSTATE_MASK 0x01000000UL
#define SETTINGS_REG_DBGAIOC0_VCOSSTATE_MASK 0x10000000UL

/* Playback and recording state */
#define SETTINGS_REG_DBGAUDIO0_RECSTATE_OFFS 24
#define SETTINGS_REG_DBGAUDIO0_RECSTATE_MASK 0x0F000000UL
#define SETTINGS_REG_DBGAUDIO0_RECSTATE_OFF_ENUM 0
#define SETTINGS_REG_DBGAUDIO0_RECSTATE_START_ENUM 1
#define SETTINGS_REG_DBGAUDIO0_RECSTATE_RUN_ENUM 2
#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_OFFS 28
#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_MASK 0xF0000000UL
#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_OFF_ENUM 0
#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_START_ENUM 1
#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_RUN_ENUM 2

/* Audio debug register 1 */
#define SETTINGS_REG_DBGAUDIO1 0xD1
#define SETTINGS_REG_DBGAUDIO1_DEFAULT 0

/* Audio debug register 2 */
#define SETTINGS_REG_DBGAUDIO2 0xD2
#define SETTINGS_REG_DBGAUDIO2_DEFAULT 0
/* Recording samplerate */
#define SETTINGS_REG_DBGAUDIO2_RECRATE_OFFS 0
#define SETTINGS_REG_DBGAUDIO2_RECRATE_MASK 0xFFFFFFFFUL

/* Audio debug register 3 */
#define SETTINGS_REG_DBGAUDIO3 0xD3
#define SETTINGS_REG_DBGAUDIO3_DEFAULT 0
/* Recording volume (master and first channel) */
#define SETTINGS_REG_DBGAUDIO3_RECVOL0_OFFS 0
#define SETTINGS_REG_DBGAUDIO3_RECVOL0_MASK 0x0000FFFFUL
#define SETTINGS_REG_DBGAUDIO3_RECVOL1_OFFS 16
#define SETTINGS_REG_DBGAUDIO3_RECVOL1_MASK 0xFFFF0000UL

/* TODO: D4, D5, D6 -> Recording buffer levels (avg/min/max) */

/* Audio debug register 4 */
#define SETTINGS_REG_DBGAUDIO4 0xD4
#define SETTINGS_REG_DBGAUDIO4_DEFAULT 0

/* Audio debug register 5 */
#define SETTINGS_REG_DBGAUDIO5 0xD5
#define SETTINGS_REG_DBGAUDIO5_DEFAULT 0

/* Audio debug register 6 */
#define SETTINGS_REG_DBGAUDIO6 0xD6
#define SETTINGS_REG_DBGAUDIO6_DEFAULT 0

/* Audio debug register 7 */
#define SETTINGS_REG_DBGAUDIO7 0xD7
#define SETTINGS_REG_DBGAUDIO7_DEFAULT 0

/* Audio debug register 8 */
#define SETTINGS_REG_DBGAUDIO8 0xD8
#define SETTINGS_REG_DBGAUDIO8_DEFAULT 0
/* Playback samplerate */
#define SETTINGS_REG_DBGAUDIO8_PLAYRATE_OFFS 0
#define SETTINGS_REG_DBGAUDIO8_PLAYRATE_MASK 0xFFFFFFFFUL

/* Audio debug register 9 */
#define SETTINGS_REG_DBGAUDIO9 0xD9
#define SETTINGS_REG_DBGAUDIO9_DEFAULT 0
/* Playback volume (master and first channel) */
#define SETTINGS_REG_DBGAUDIO9_PLAYVOL0_OFFS 0
#define SETTINGS_REG_DBGAUDIO9_PLAYVOL0_MASK 0x0000FFFFUL
#define SETTINGS_REG_DBGAUDIO9_PLAYVOL1_OFFS 16
#define SETTINGS_REG_DBGAUDIO9_PLAYVOL1_MASK 0xFFFF0000UL

/* Audio debug register 10 */
#define SETTINGS_REG_DBGAUDIO10 0xDA
#define SETTINGS_REG_DBGAUDIO10_DEFAULT 0
/* Average playback buffer level */
#define SETTINGS_REG_DBGAUDIO10_PLAYBUFAVG_OFFS 0
#define SETTINGS_REG_DBGAUDIO10_PLAYBUFAVG_MASK 0x0000FFFFUL

/* Audio debug register 11 */
#define SETTINGS_REG_DBGAUDIO11 0xDB
#define SETTINGS_REG_DBGAUDIO11_DEFAULT 0
/* Minimum playback buffer level */
#define SETTINGS_REG_DBGAUDIO11_PLAYBUFMIN_OFFS 0
#define SETTINGS_REG_DBGAUDIO11_PLAYBUFMIN_MASK 0x0000FFFFUL

/* Audio debug register 12 */
#define SETTINGS_REG_DBGAUDIO12 0xDC
#define SETTINGS_REG_DBGAUDIO12_DEFAULT 0
/* Maximum playback buffer level */
#define SETTINGS_REG_DBGAUDIO12_PLAYBUFMAX_OFFS 0
#define SETTINGS_REG_DBGAUDIO12_PLAYBUFMAX_MASK 0x0000FFFFUL

/* Audio debug register 13 */
#define SETTINGS_REG_DBGAUDIO13 0xDD
#define SETTINGS_REG_DBGAUDIO13_DEFAULT 0
/* Average UAC2.0 Feedback Value since last playback */
#define SETTINGS_REG_DBGAUDIO13_PLAYFBAVG_OFFS 0
#define SETTINGS_REG_DBGAUDIO13_PLAYFBAVG_MASK 0xFFFFFFFFUL

/* Audio debug register 14 */
#define SETTINGS_REG_DBGAUDIO14 0xDE
#define SETTINGS_REG_DBGAUDIO14_DEFAULT 0
/* Minimum UAC2.0 Feedback Value since last playback */
#define SETTINGS_REG_DBGAUDIO14_PLAYFBMIN_OFFS 0
#define SETTINGS_REG_DBGAUDIO14_PLAYFBMIN_MASK 0xFFFFFFFFUL

/* Audio debug register 15 */
#define SETTINGS_REG_DBGAUDIO15 0xDF
#define SETTINGS_REG_DBGAUDIO15_DEFAULT 0
/* Maximum UAC2.0 Feedback Value since last playback */
#define SETTINGS_REG_DBGAUDIO15_PLAYFBMAX_OFFS 0
#define SETTINGS_REG_DBGAUDIO15_PLAYFBMAX_MASK 0xFFFFFFFFUL



void Settings_Init();
uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize);
uint8_t Settings_RegRead(uint8_t address, uint8_t * buffer, uint8_t bufsize);
Expand Down

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