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[+] Add cdc_afifo system verilog implementation build #60: Commit 6bdfd61 pushed by sergeykhbr
November 15, 2024 14:34 5m 41s master
master
November 15, 2024 14:34 5m 41s
[*] Try debugger with the latest systemc library and fix the followin… build #59: Commit 9f29cfc pushed by sergeykhbr
November 15, 2024 11:54 5m 38s master
master
November 15, 2024 11:54 5m 38s
[!] fix sv names missmatch after rtlgen upgrade build #58: Commit b5de93b pushed by sergeykhbr
October 30, 2024 19:07 5m 38s master
master
October 30, 2024 19:07 5m 38s
[+] Update systemVerilog rtl generator to support multiple clock and … build #57: Commit 0874c3a pushed by sergeykhbr
October 30, 2024 16:29 5m 43s master
master
October 30, 2024 16:29 5m 43s
[*] Update SystemC model after rtlgen upgrade to support multiple res… build #56: Commit 70ede88 pushed by sergeykhbr
October 28, 2024 21:31 5m 38s master
master
October 28, 2024 21:31 5m 38s
[*] minor syntax changes in systemc build #55: Commit adefeb9 pushed by sergeykhbr
December 21, 2023 10:54 5m 44s master
master
December 21, 2023 10:54 5m 44s
[*] Add .read() operation for an input and signals variables in syste… build #54: Commit a3589d9 pushed by sergeykhbr
December 15, 2023 20:25 5m 25s master
master
December 15, 2023 20:25 5m 25s
Merge branch 'master' of https://github.com/sergeykhbr/riscv_vhdl build #53: Commit 434a100 pushed by sergeykhbr
December 15, 2023 18:34 5m 46s master
master
December 15, 2023 18:34 5m 46s
[*] Comment fixed build #52: Commit aec40dd pushed by sergeykhbr
December 15, 2023 11:03 5m 32s master
master
December 15, 2023 11:03 5m 32s
[+] Fix in rtlgen to add skipped include statement with target_cfg.h … build #51: Commit 10766a1 pushed by sergeykhbr
December 12, 2023 20:45 5m 28s master
master
December 12, 2023 20:45 5m 28s
[*] minor changes: packages import order has been changed build #50: Commit 231ce17 pushed by sergeykhbr
December 10, 2023 21:17 5m 37s master
master
December 10, 2023 21:17 5m 37s
[!] Fix verilog build errors. Run asic_sim successfully build #49: Commit ac92e5b pushed by sergeykhbr
December 10, 2023 21:00 5m 48s master
master
December 10, 2023 21:00 5m 48s
[*] update systemc with the latest rtlgen generated code: 0ull consta… build #48: Commit 0a8ed6d pushed by sergeykhbr
December 10, 2023 20:41 5m 15s master
master
December 10, 2023 20:41 5m 15s
[*] regenerate system verilog with the new version of rtlgen generator build #47: Commit f179595 pushed by sergeykhbr
December 10, 2023 20:35 5m 15s master
master
December 10, 2023 20:35 5m 15s
[+] Add constructor to initialize all member variable for the interfa… build #46: Commit b3ee236 pushed by sergeykhbr
December 9, 2023 22:17 5m 49s master
master
December 9, 2023 22:17 5m 49s
[*] rtlgen generator was significantly updated, new structure, better… build #45: Commit e768492 pushed by sergeykhbr
December 9, 2023 21:37 6m 5s master
master
December 9, 2023 21:37 6m 5s