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Remove metadata from target specs
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This metadata was leftover from the builtin targets they are based on.

Signed-off-by: Nick Spinale <[email protected]>
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nspin committed Sep 19, 2024
1 parent 5f6d5da commit 33e5beb
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Showing 27 changed files with 107 additions and 105 deletions.
4 changes: 3 additions & 1 deletion crates/sel4-generate-target-specs/src/main.rs
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Expand Up @@ -223,7 +223,9 @@ impl Context {
}

fn builtin(triple: &str) -> Target {
Target::expect_builtin(&TargetTriple::from_triple(triple))
let mut target = Target::expect_builtin(&TargetTriple::from_triple(triple));
target.metadata = Default::default();
target
}

fn all_target_specs() -> BTreeMap<String, Target> {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-minimal.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-resettable-minimal.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit-resettable.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-microkit.json
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Expand Up @@ -13,10 +13,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"pre-link-args": {
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8 changes: 4 additions & 4 deletions support/targets/aarch64-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@
"llvm-target": "aarch64-unknown-none",
"max-atomic-width": 128,
"metadata": {
"description": "Bare ARM64, hardfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"pre-link-args": {
"gnu-lld": [
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8 changes: 4 additions & 4 deletions support/targets/armv7a-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "armv7a-none-eabi",
"max-atomic-width": 64,
"metadata": {
"description": "Bare Armv7-A",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/armv7a-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "armv7a-none-eabi",
"max-atomic-width": 64,
"metadata": {
"description": "Bare Armv7-A",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imac-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imac-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"target-pointer-width": "32"
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8 changes: 4 additions & 4 deletions support/targets/riscv32imafc-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAFC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv32imafc-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv32",
"max-atomic-width": 32,
"metadata": {
"description": "Bare RISC-V (RV32IMAFC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"target-pointer-width": "32"
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit-minimal.json
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Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit-resettable.json
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-microkit.json
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64gc-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAFDC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit-resettable.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-microkit.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"relocation-model": "static",
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8 changes: 4 additions & 4 deletions support/targets/riscv64imac-sel4.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "riscv64",
"max-atomic-width": 64,
"metadata": {
"description": "Bare RISC-V (RV64IMAC ISA)",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"relocation-model": "static",
"supported-sanitizers": [
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8 changes: 4 additions & 4 deletions support/targets/x86_64-sel4-minimal.json
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,10 @@
"llvm-target": "x86_64-unknown-none-elf",
"max-atomic-width": 64,
"metadata": {
"description": "Freestanding/bare-metal x86_64 softfloat",
"host_tools": false,
"std": false,
"tier": 2
"description": null,
"host_tools": null,
"std": null,
"tier": null
},
"panic-strategy": "abort",
"plt-by-default": false,
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