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target specs: stricter checks for LLVM ABI values, and correlate that with cfg(target_abi) #153769

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Merged
rust-bors merged 2 commits into from
Mar 14, 2026
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target specs: stricter checks for LLVM ABI values, and correlate that with cfg(target_abi) #153769

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target specs: tighten checks for llvm_abiname and llvm_floatabi, and …
RalfJung Mar 12, 2026
2662303
mips: require LLVM ABI to be explicitly set, but also allow n32
RalfJung Mar 12, 2026
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11 changes: 3 additions & 8 deletions compiler/rustc_codegen_ssa/src/back/metadata.rs
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Expand Up @@ -294,18 +294,13 @@ pub(super) fn elf_e_flags(architecture: Architecture, sess: &Session) -> u32 {
_ => elf::EF_MIPS_ARCH_64R2,
};

// If the ABI is explicitly given, use it, or default to O32 on 32-bit MIPS,
// which is the only "true" 32-bit option that LLVM supports.
// Use the explicitly given ABI.
match sess.target.options.llvm_abiname.as_ref() {
"o32" if is_32bit => e_flags |= elf::EF_MIPS_ABI_O32,
"n32" if !is_32bit => e_flags |= elf::EF_MIPS_ABI2,
"n64" if !is_32bit => {}
"" if is_32bit => e_flags |= elf::EF_MIPS_ABI_O32,
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@RalfJung RalfJung Mar 14, 2026

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Now that all MIPS targets must set an LLVM abi, we don't need a default here any more.

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@madsmtm madsmtm Mar 14, 2026

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Haha, I was just going to comment on that

"" => sess.dcx().fatal("LLVM ABI must be specified for 64-bit MIPS targets"),
s if is_32bit => {
sess.dcx().fatal(format!("invalid LLVM ABI `{}` for 32-bit MIPS target", s))
}
s => sess.dcx().fatal(format!("invalid LLVM ABI `{}` for 64-bit MIPS target", s)),
// The rest is invalid (which is already ensured by the target spec check).
s => bug!("invalid LLVM ABI `{}` for MIPS target", s),
};

if sess.target.options.relocation_model != RelocModel::Static {
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7 changes: 6 additions & 1 deletion compiler/rustc_target/src/spec/base/apple/mod.rs
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Expand Up @@ -127,7 +127,12 @@ pub(crate) fn base(
let link_env_remove = link_env_remove(&os);
let unversioned_llvm_target = unversioned_llvm_target(&os, arch, env);
let mut opts = TargetOptions {
llvm_floatabi: Some(FloatAbi::Hard),
llvm_floatabi: if arch.target_arch() == crate::spec::Arch::Arm {
Some(FloatAbi::Hard)
} else {
// `llvm_floatabi` makes no sense on x86 and aarch64.
None
},
Comment on lines +130 to +135
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@RalfJung RalfJung Mar 12, 2026 •
edited
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@nikic just to double check -- it is correct that x86 and aarch64 ignore LLVM's FloatAbi field, right? A quick grep seems to confirm this but I don't want to accidentally break the ABI here.^^

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@madsmtm madsmtm Mar 14, 2026

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CC #134932 where the original was introduced, I think it was just an oversight there.

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@RalfJung RalfJung Mar 14, 2026 •
edited
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Oops, it was me? 🙈 Yeah, definitely an oversight, I didn't realize that this would also affect non-ARM targets.

os,
env: env.target_env(),
abi: env.target_abi(),
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287 changes: 248 additions & 39 deletions compiler/rustc_target/src/spec/mod.rs
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mips_mti_none_elf.rs
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Expand Up @@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
endian: Endian::Big,
cpu: "mips32r2".into(),

llvm_abiname: "o32".into(),
max_atomic_width: Some(32),

features: "+mips32r2,+soft-float,+noabicalls".into(),
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mips_unknown_linux_gnu.rs
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Expand Up @@ -18,6 +18,7 @@ pub(crate) fn target() -> Target {
endian: Endian::Big,
cpu: "mips32r2".into(),
features: "+mips32r2,+fpxx,+nooddspreg".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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7 changes: 6 additions & 1 deletion compiler/rustc_target/src/spec/targets/mips_unknown_linux_musl.rs
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Expand Up @@ -18,6 +18,11 @@ pub(crate) fn target() -> Target {
pointer_width: 32,
data_layout: "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64".into(),
arch: Arch::Mips,
options: TargetOptions { endian: Endian::Big, mcount: "_mcount".into(), ..base },
options: TargetOptions {
endian: Endian::Big,
llvm_abiname: "o32".into(),
mcount: "_mcount".into(),
..base
},
}
}
1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mips_unknown_linux_uclibc.rs
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Expand Up @@ -18,6 +18,7 @@ pub(crate) fn target() -> Target {
endian: Endian::Big,
cpu: "mips32r2".into(),
features: "+mips32r2,+soft-float".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_mti_none_elf.rs
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Expand Up @@ -24,6 +24,7 @@ pub(crate) fn target() -> Target {
endian: Endian::Little,
cpu: "mips32r2".into(),

llvm_abiname: "o32".into(),
max_atomic_width: Some(32),

features: "+mips32r2,+soft-float,+noabicalls".into(),
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_sony_psp.rs
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Expand Up @@ -36,6 +36,7 @@ pub(crate) fn target() -> Target {

// PSP does not support trap-on-condition instructions.
llvm_args: cvs!["-mno-check-zero-division"],
llvm_abiname: "o32".into(),
pre_link_args,
link_script: Some(LINKER_SCRIPT.into()),
..Default::default()
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_unknown_linux_gnu.rs
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Expand Up @@ -16,6 +16,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
cpu: "mips32r2".into(),
features: "+mips32r2,+fpxx,+nooddspreg".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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2 changes: 1 addition & 1 deletion compiler/rustc_target/src/spec/targets/mipsel_unknown_linux_musl.rs
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Expand Up @@ -16,6 +16,6 @@ pub(crate) fn target() -> Target {
pointer_width: 32,
data_layout: "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64".into(),
arch: Arch::Mips,
options: TargetOptions { mcount: "_mcount".into(), ..base },
options: TargetOptions { llvm_abiname: "o32".into(), mcount: "_mcount".into(), ..base },
}
}
1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_unknown_linux_uclibc.rs
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Expand Up @@ -16,6 +16,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
cpu: "mips32r2".into(),
features: "+mips32r2,+soft-float".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_unknown_netbsd.rs
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Expand Up @@ -20,6 +20,7 @@ pub(crate) fn target() -> Target {
arch: Arch::Mips,
options: TargetOptions {
features: "+soft-float".into(),
llvm_abiname: "o32".into(),
mcount: "__mcount".into(),
endian: Endian::Little,
..base
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsel_unknown_none.rs
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Expand Up @@ -23,6 +23,7 @@ pub(crate) fn target() -> Target {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
cpu: "mips32r2".into(),
features: "+mips32r2,+soft-float,+noabicalls".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
linker: Some("rust-lld".into()),
panic_strategy: PanicStrategy::Abort,
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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsisa32r6_unknown_linux_gnu.rs
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Expand Up @@ -18,6 +18,7 @@ pub(crate) fn target() -> Target {
endian: Endian::Big,
cpu: "mips32r6".into(),
features: "+mips32r6".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/targets/mipsisa32r6el_unknown_linux_gnu.rs
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Expand Up @@ -16,6 +16,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
cpu: "mips32r6".into(),
features: "+mips32r6".into(),
llvm_abiname: "o32".into(),
max_atomic_width: Some(32),
mcount: "_mcount".into(),

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