Verifying FOSS HDL-synthesizers

The aim of this project is to provide feedback about things supported by the vendor EDA tools, which presents issues for Yosys, GHDL or ghdl-yosys-plugin. This is performed, running the tools against several examples from different sources:

• xilinx: Verilog and VHDL examples for ISE and Vivado, provided by Xilinx.
• FPGADesignElements: a online book containing a library of FPGA Verilog design modules.

Firstly, the examples are checked with commercial tools such as ISE, Vivado and Quartus, to check if they are synthesizable. Secondly, they are analyzed with tools like iVerilog and GHDL to detect non-standard constructions. Then, the tools under test are employed. If an issue is detected, it is reported and the file is ignored until fixed. To simplify tools and options handling, fpga-hdl2bit from the PyFPGA project is used (when supported).

A Dockerfile, based on ghdl/synth:beta from the ghdl/docker project (which supports the three tools under test), is provided. It is employed for the CI of the repository and can be used to run in any GNU/Linux with Docker installed on:

• make build creates the needed Docker image.
• bash helpers/docker_run.sh make clean-all to clean the generated files of a previous run.
• make prepare downloads the examples (they are not part of the repository).
• bash helpers/docker_run.sh make verify-yosys to verify yosys.
• bash helpers/docker_run.sh make verify-ghdl to verify ghdl --synth.
• bash helpers/docker_run.sh make verify-ghdl-yosys to verify ghdl-yosys-plugin.

License

This project is distributed under ISC license.