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Use pre-v5 enum names which are now supported by compatibility macros. #4691

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merged 9 commits into from
Oct 29, 2024
Merged

Use pre-v5 enum names which are now supported by compatibility macros. #4691

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b47a74a
Use pre-v5 enum names which are now supported by compatibility macros.
Rot127 Oct 25, 2024
d74ac78
Merge branch 'dev' into capstone-pre-v6-build-fix
XVilka Oct 25, 2024
c681017
Bump CS version to newest next
Rot127 Oct 26, 2024
100b056
Run clang-format
Rot127 Oct 26, 2024
72192b0
Remove Capstone v6 job until v6 patch release is out.
Rot127 Oct 26, 2024
641b8bd
Check for support of enum compare/conversion warnings.
Rot127 Oct 26, 2024
73e7288
Bump to newest next
Rot127 Oct 28, 2024
6102c53
More warning checks
Rot127 Oct 28, 2024
c514608
Update capstone-next.wrap
XVilka Oct 29, 2024
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10 changes: 0 additions & 10 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -160,16 +160,6 @@ jobs:
timeout: 45
cflags: "-Wno-cpp"
allow_failure: true
- name: capstone-v6
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_capstone_version=v6 --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
cflags: "-Wno-cpp"
allow_failure: false
- name: no-gpl-code
os: ubuntu-22.04
build_system: meson
Expand Down
6 changes: 6 additions & 0 deletions librz/arch/isa/arm/arm_accessors32.h
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Expand Up @@ -7,8 +7,14 @@
* cs_insn *insn
*/

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand Down
9 changes: 8 additions & 1 deletion librz/arch/isa/arm/arm_cs.h
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Expand Up @@ -5,8 +5,15 @@
#define RZ_ARM_CS_H

#include <rz_analysis.h>

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand All @@ -21,7 +28,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
Expand Down
7 changes: 7 additions & 0 deletions librz/arch/isa/arm/arm_esil32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,15 @@
// SPDX-License-Identifier: LGPL-3.0-only

#include <rz_analysis.h>

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand Down
42 changes: 24 additions & 18 deletions librz/arch/isa/arm/arm_esil64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,14 @@

#include <rz_analysis.h>

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand All @@ -15,71 +21,71 @@
#define MEMBASE64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.base))
#define MEMINDEX64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.index))

RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type) {
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type) {
const char *close_cond[2];
close_cond[0] = "";
close_cond[1] = ",}";
int close_type = 0;
switch (cond_type) {
case ARM64CC_EQ:
case ARM64_CC_EQ:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,?{,");
break;
case ARM64CC_NE:
case ARM64_CC_NE:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,?{,");
break;
case ARM64CC_HS:
case ARM64_CC_HS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,?{,");
break;
case ARM64CC_LO:
case ARM64_CC_LO:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,?{,");
break;
case ARM64CC_MI:
case ARM64_CC_MI:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,?{,");
break;
case ARM64CC_PL:
case ARM64_CC_PL:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,!,?{,");
break;
case ARM64CC_VS:
case ARM64_CC_VS:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,?{,");
break;
case ARM64CC_VC:
case ARM64_CC_VC:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,!,?{,");
break;
case ARM64CC_HI:
case ARM64_CC_HI:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,");
break;
case ARM64CC_LS:
case ARM64_CC_LS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,");
break;
case ARM64CC_GE:
case ARM64_CC_GE:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,");
break;
case ARM64CC_LT:
case ARM64_CC_LT:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,?{,");
break;
case ARM64CC_GT:
case ARM64_CC_GT:
// zf == 0 && nf == vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,");
break;
case ARM64CC_LE:
case ARM64_CC_LE:
// zf == 1 || nf != vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,");
break;
case ARM64CC_AL:
case ARM64_CC_AL:
// always executed
break;
default:
Expand Down Expand Up @@ -129,7 +135,7 @@ static int arm64_reg_width(int reg) {
return 64;
}

static int decode_sign_ext(aarch64_extender extender) {
static int decode_sign_ext(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
case ARM64_EXT_UXTH:
Expand All @@ -153,7 +159,7 @@ static int decode_sign_ext(aarch64_extender extender) {

#define EXT64(x) decode_sign_ext(insn->detail->arm64.operands[x].ext)

static const char *decode_shift_64(aarch64_shifter shift) {
static const char *decode_shift_64(arm64_shifter shift) {
const char *E_OP_SR = ">>";
const char *E_OP_SL = "<<";
const char *E_OP_RR = ">>>";
Expand Down
6 changes: 6 additions & 0 deletions librz/arch/isa/arm/arm_il32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,14 @@
#include <rz_analysis.h>
#include <rz_util/rz_assert.h>

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand Down
36 changes: 21 additions & 15 deletions librz/arch/isa/arm/arm_il64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,14 @@

#include <rz_analysis.h>

#if CC_SUPPORTS_W_ENUM_COMPARE
#pragma GCC diagnostic ignored "-Wenum-compare"
#endif

#ifdef CC_SUPPORTS_W_ENUM_CONVERION
#pragma GCC diagnostic ignored "-Wenum-conversion"
#endif

#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>

Expand Down Expand Up @@ -39,35 +45,35 @@ static const char *regs_bound[] = {
* IL for arm64 condition
* unconditional is returned as NULL (rather than true), for simpler code
*/
static RzILOpBool *cond(ARM64CC_CondCode c) {
static RzILOpBool *cond(arm64_cc c) {
switch (c) {
case ARM64CC_EQ:
case ARM64_CC_EQ:
return VARG("zf");
case ARM64CC_NE:
case ARM64_CC_NE:
return INV(VARG("zf"));
case ARM64CC_HS:
case ARM64_CC_HS:
return VARG("cf");
case ARM64CC_LO:
case ARM64_CC_LO:
return INV(VARG("cf"));
case ARM64CC_MI:
case ARM64_CC_MI:
return VARG("nf");
case ARM64CC_PL:
case ARM64_CC_PL:
return INV(VARG("nf"));
case ARM64CC_VS:
case ARM64_CC_VS:
return VARG("vf");
case ARM64CC_VC:
case ARM64_CC_VC:
return INV(VARG("vf"));
case ARM64CC_HI:
case ARM64_CC_HI:
return AND(VARG("cf"), INV(VARG("zf")));
case ARM64CC_LS:
case ARM64_CC_LS:
return OR(INV(VARG("cf")), VARG("zf"));
case ARM64CC_GE:
case ARM64_CC_GE:
return INV(XOR(VARG("nf"), VARG("vf")));
case ARM64CC_LT:
case ARM64_CC_LT:
return XOR(VARG("nf"), VARG("vf"));
case ARM64CC_GT:
case ARM64_CC_GT:
return INV(OR(XOR(VARG("nf"), VARG("vf")), VARG("zf")));
case ARM64CC_LE:
case ARM64_CC_LE:
return OR(XOR(VARG("nf"), VARG("vf")), VARG("zf"));
default:
return NULL;
Expand Down
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