Skip to content

Commit

Permalink
fix: tricore il and test
Browse files Browse the repository at this point in the history
  • Loading branch information
@imbillow
imbillow committed Nov 2, 2024
1 parent e470484 commit 8d0e5a7
Show file tree
Hide file tree
Showing 3 changed files with 72 additions and 101 deletions.
125 changes: 49 additions & 76 deletions librz/arch/isa/tricore/tricore_il.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1117,27 +1117,15 @@ static RzAnalysisLiftedILOp addr_circular_2(ut8 B, RzILOpPure *(*g)(RzILOpPure *
SETG(a, APPEND(LOADW(B, VARL("EA4")), LOADW(B, VARL("EA")))));
}

static RzAnalysisLiftedILOp ld_sc(RzAsmTriCoreContext *ctx, ut8 B, RzILOpPure *(*f)(RzILOpPure *, ut32), const char rprefx) {
if (rprefx == 'a') {
return SEQ2(
SETL("EA", ADD(VARG(/*a10*/ TriCoreREGs[10]), U32(I(0) * 4))),
SETG_EA("a15", B, f));
}
if (rprefx == 'd') {
return SEQ2(
SETL("EA", ADD(VARG(/*d10*/ TriCoreREGs[16 + 10]), U32(I(0) * 4))),
SETG_EA("d15", B, f));
}
rz_warn_if_reached();
return NULL;
static RzAnalysisLiftedILOp ld_sc(RzAsmTriCoreContext *ctx, ut8 B, RzILOpPure *(*f)(RzILOpPure *, ut32)) {
TriCoreMem m = M(1);
return SEQ2(
SETL("EA", ADD(VARG(m.reg), U32(m.disp * 4))),
SETG_EA(R(0), B, f));
}
static RzAnalysisLiftedILOp st_sc(RzAsmTriCoreContext *ctx, ut8 B, const char rprefx) {
unsigned const8 = I(0);
if (rprefx == 'a' || rprefx == 'd') {
return STOREW(ADD(VARG("a10"), U32(B / 8 * const8)), UNSIGNED(B, VARG(rprefx == 'a' ? "a15" : "d15")));
}
rz_warn_if_reached();
return NULL;
static RzAnalysisLiftedILOp st_sc(RzAsmTriCoreContext *ctx, ut8 B) {
TriCoreMem m = M(0);
return STOREW(ADD(VARG(m.reg), U32(B / 8 * m.disp)), UNSIGNED(B, VARG(R(1))));

Check failure

Code scanning / CodeQL

Multiplication result converted to larger type High

Multiplication result may overflow 'unsigned int' before it is converted to 'unsigned long long'.
}

static RzAnalysisLiftedILOp ld_slr(RzAsmTriCoreContext *ctx, ut8 B, RzILOpPure *(*f)(RzILOpPure *, ut32)) {
Expand All @@ -1154,17 +1142,17 @@ static RzAnalysisLiftedILOp ld_slr_post_increment(RzAsmTriCoreContext *ctx, ut8
}

static RzAnalysisLiftedILOp ld_slro(RzAsmTriCoreContext *ctx, ut8 B, RzILOpPure *(*f)(RzILOpPure *, ut32)) {
TriCoreMem m = M(0);
TriCoreMem m = M(1);
return SEQ2(
SETL("EA", ADD(VARG("a15"), U32(4 * m.disp))),
SETG_EA(m.reg, B, f));
SETL("EA", ADD(VARG(m.reg), U32(4 * m.disp))),
SETG_EA(R(0), B, f));
}

static RzAnalysisLiftedILOp ld_sro(RzAsmTriCoreContext *ctx, ut8 B, RzILOpPure *(*f)(RzILOpPure *, ut32)) {
TriCoreMem m = M(0);
TriCoreMem m = M(1);
return SEQ2(
SETL("EA", ADD(VARG(m.reg), U32(4 * m.disp))),
SETG_EA("a15", B, f));
SETG_EA(R(0), B, f));
}
static RzAnalysisLiftedILOp st_sro(RzAsmTriCoreContext *ctx, ut8 B) {
TriCoreMem m = M(0);
Expand All @@ -1186,9 +1174,8 @@ static RzAnalysisLiftedILOp st_ssr_post_incr(RzAsmTriCoreContext *ctx, ut8 B) {
SETG(b, ADD(VARG(b), U32(B / 8))));
}
static RzAnalysisLiftedILOp st_ssro(RzAsmTriCoreContext *ctx, ut8 B) {
const char *a = R(1);
unsigned const4 = I(0);
return STOREW(ADD(VARG("a15"), U32(B / 8 * const4)), UNSIGNED(B, VARG(a)));
TriCoreMem m = M(0);
return STOREW(ADD(VARG(m.reg), U32(B / 8 * m.disp)), UNSIGNED(B, VARG(R(1))));

Check failure

Code scanning / CodeQL

Multiplication result converted to larger type High

Multiplication result may overflow 'unsigned int' before it is converted to 'unsigned long long'.
}

static RzAnalysisLiftedILOp load_lower_context() {
Expand Down Expand Up @@ -1376,7 +1363,7 @@ lift_ld_op(RzAsmTriCoreContext *ctx) {
break;
}
case /*LD.A BOL*/ 0x99: return ld_base_long_offset(ctx, Word_b, NULL);
case /*LD.A SC*/ 0xd8: return ld_sc(ctx, Word_b, NULL, 'a');
case /*LD.A SC*/ 0xd8: return ld_sc(ctx, Word_b, NULL);
case /*LD.A SLR*/ 0xd4: return ld_slr(ctx, Word_b, NULL);
case /*LD.A SLR*/ 0xc4: return ld_slr_post_increment(ctx, Word_b, NULL);
case /*LD.A SLRO*/ 0xc8: return ld_slro(ctx, Word_b, NULL);
Expand All @@ -1394,7 +1381,7 @@ lift_ld_op(RzAsmTriCoreContext *ctx) {
case /*LD.H SRO*/ 0x8c: return ld_sro(ctx, HalfWord_b, SEXT32);
case /*LD.HU BOL*/ 0xb9: return ld_base_long_offset(ctx, HalfWord_b, ZEXT32);
case /*LD.W BOL*/ 0x19: return ld_base_long_offset(ctx, Word_b, NULL);
case /*LD.W SC*/ 0x58: return ld_sc(ctx, Word_b, NULL, 'd');
case /*LD.W SC*/ 0x58: return ld_sc(ctx, Word_b, NULL);
case /*LD.W SLR*/ 0x54: return ld_slr(ctx, Word_b, NULL);
case /*LD.W SLR*/ 0x44: return ld_slr_post_increment(ctx, Word_b, NULL);
case /*LD.W SLRO*/ 0x48: return ld_slro(ctx, Word_b, NULL);
Expand Down Expand Up @@ -1510,7 +1497,7 @@ lift_st_op(RzAsmTriCoreContext *ctx) {
break;
}
case /*ST.A BOL*/ 0xb5: return st_base_long_offset(ctx, Word_b);
case /*ST.A SC*/ 0xf8: return st_sc(ctx, Word_b, 'a');
case /*ST.A SC*/ 0xf8: return st_sc(ctx, Word_b);
case /*ST.A SRO*/ 0xec: return st_sro(ctx, Word_b);
case /*ST.A SSR*/ 0xf4: return st_ssr(ctx, Word_b);
case /*ST.A SSR(post)*/ 0xe4: return st_ssr_post_incr(ctx, Word_b);
Expand All @@ -1529,7 +1516,7 @@ lift_st_op(RzAsmTriCoreContext *ctx) {
case /*ST.H SSRO*/ 0xa8: return st_ssro(ctx, Word_b);

case /*ST.W BOL*/ 0x59: return st_base_long_offset(ctx, Word_b);
case /*ST.W SC*/ 0x78: return st_sc(ctx, Word_b, 'd');
case /*ST.W SC*/ 0x78: return st_sc(ctx, Word_b);
case /*ST.W SRO*/ 0x6c: return st_sro(ctx, Word_b);
case /*ST.W SSR*/ 0x74: return st_ssr(ctx, Word_b);
case /*ST.W SSR(post)*/ 0x64: return st_ssr_post_incr(ctx, Word_b);
Expand Down Expand Up @@ -2100,11 +2087,11 @@ static RzAnalysisLiftedILOp lift_add(RzAsmTriCoreContext *ctx) {
break;
}
case 0xc2: return packed_op2_sov(R(0), VARG(R(0)), sign_ext32_bv(I(1), 4), Word_b, rz_il_op_new_add, NULL);
case 0x92: return packed_op2_sov(R(0), VARG("d15"), sign_ext32_bv(I(1), 4), Word_b, rz_il_op_new_add, NULL);
case 0x9a: return packed_op2_sov("d15", VARG(R(0)), sign_ext32_bv(I(1), 4), Word_b, rz_il_op_new_add, NULL);
case 0x92:
case 0x9a: return packed_op2_sov(R(0), VARG(R(1)), sign_ext32_bv(I(2), 4), Word_b, rz_il_op_new_add, NULL);
case 0x42: return packed_op2_sov(R(0), VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_add, NULL);
case 0x12: return packed_op2_sov(R(0), VARG("d15"), VARG(R(1)), Word_b, rz_il_op_new_add, NULL);
case 0x1a: return packed_op2_sov("d15", VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_add, NULL);
case 0x12:
case 0x1a: return packed_op2_sov(R(0), VARG(R(1)), VARG(R(2)), Word_b, rz_il_op_new_add, NULL);
case 0x22: return packed_op2_sov(R(0), VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_add, ssov);
default: break;
}
Expand Down Expand Up @@ -2148,8 +2135,8 @@ static RzAnalysisLiftedILOp lift_cadd(RzAsmTriCoreContext *ctx) {
}
break;
}
case /*CADD (SRC)*/ 0x8a: return e_cadd(R(0), NON_ZERO(VARG("d15")), VARG(R(0)), sign_ext32_bv(I(1), 4));
case /*CADDN (SRC)*/ 0xca: return e_cadd(R(0), IS_ZERO(VARG("d15")), VARG(R(0)), sign_ext32_bv(I(1), 4));
case /*CADD (SRC)*/ 0x8a: return e_cadd(R(0), NON_ZERO(VARG(R(1))), VARG(R(0)), sign_ext32_bv(I(2), 4));
case /*CADDN (SRC)*/ 0xca: return e_cadd(R(0), IS_ZERO(VARG(R(1))), VARG(R(0)), sign_ext32_bv(I(2), 4));
default: break;
}
rz_warn_if_reached();
Expand Down Expand Up @@ -3346,9 +3333,9 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case 0xdf: return BRANCH(NE(VARG(R(0)), sign_ext32_bv(I(1), 4)), JMP(U32(I(2))), NOP());
case 0x5f: return BRANCH(NE(VARG(R(0)), VARG(R(1))), JMP(U32(I(2))), NOP());
case 0x5e:
case 0xde: return BRANCH(NE(VARG("d15"), sign_ext32_bv(I(0), 4)), JMP(U32(I(1))), NOP());
case 0xde: return BRANCH(NE(VARG(R(0)), sign_ext32_bv(I(1), 4)), JMP(U32(I(2))), NOP());
case 0x7e:
case 0xfe: return BRANCH(NE(VARG("d15"), VARG(R(0))), JMP(U32(I(1))), NOP());
case 0xfe: return BRANCH(NE(VARG(R(0)), VARG(R(1))), JMP(U32(I(2))), NOP());
default: break;
}
break;
Expand Down Expand Up @@ -3387,28 +3374,19 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
}
break;
case TRICORE_INS_JNZ_T:
if (OPC1_BRN == 0x6f) {
return BRANCH(BIT32(VARG(R(0)), I(1)), JMP(U32(I(2))), NOP());
}
if (OPC1 == 0xae) {
return BRANCH(BIT32(VARG("d15"), I(0)), JMP(U32(I(1))), NOP());
}
return BRANCH(BIT32(VARG(R(0)), I(1)), JMP(U32(I(2))), NOP());
break;
case TRICORE_INS_JNZ:
switch (OPC1) {
case 0xee: return BRANCH(NE(VARG("d15"), U32(0)), JMP(U32(I(0))), NOP());
case 0xf6: return BRANCH(NE(VARG(R(0)), U32(0)), JMP(U32(I(1))), NOP());
default: break;
}
return BRANCH(NE(VARG(R(0)), U32(0)), JMP(U32(I(1))), NOP());
break;
case TRICORE_INS_JEQ:
switch (OPC1) {
case 0xdf: return BRANCH(EQ(VARG(R(0)), sign_ext32_bv(I(1), 4)), JMP(U32(I(2))), NOP());
case 0x5f: return BRANCH(EQ(VARG(R(0)), VARG(R(1))), JMP(U32(I(2))), NOP());
case 0x1e:
case 0x9e: return BRANCH(EQ(VARG("d15"), sign_ext32_bv(I(0), 4)), JMP(U32(I(1))), NOP());
case 0x9e: return BRANCH(EQ(VARG(R(0)), sign_ext32_bv(I(1), 4)), JMP(U32(I(2))), NOP());
case 0x3e:
case 0xbe: return BRANCH(EQ(VARG("d15"), VARG(R(0))), JMP(U32(I(1))), NOP());
case 0xbe: return BRANCH(EQ(VARG(R(0)), VARG(R(1))), JMP(U32(I(2))), NOP());
default: break;
}
break;
Expand All @@ -3431,7 +3409,7 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_JGTZ: return BRANCH(UGT(VARG(R(0)), U32(0)), JMP(U32(I(1))), NOP());
case TRICORE_INS_JZ:
switch (OPC1) {
case 0x6e: return BRANCH(EQ(VARG("d15"), U32(0)), JMP(U32(I(0))), NOP());
case 0x6e: return BRANCH(EQ(VARG(R(0)), U32(0)), JMP(U32(I(1))), NOP());
case 0x76: return BRANCH(IS_ZERO(VARG(R(0))), JMP(U32(I(1))), NOP());
default: break;
}
Expand All @@ -3444,12 +3422,7 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
}
break;
case TRICORE_INS_JZ_T: {
if (OPC1_BRN == 0x6f) {
return BRANCH(INV(BIT32(VARG(R(0)), I(1))), JMP(U32(I(2))), NOP());
}
if (OPC1 == 0x2e) {
return BRANCH(INV(BIT32(VARG("d15"), I(0))), JMP(U32(I(1))), NOP());
}
return BRANCH(INV(BIT32(VARG(R(0)), I(1))), JMP(U32(I(2))), NOP());
break;
}
case TRICORE_INS_LDLCX:
Expand Down Expand Up @@ -3511,11 +3484,11 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case /*MOV.D SRR*/ 0x80: return SETG(R(0), VARG(R(1)));
case /*ADD.A SRC*/ 0xb0: return SETG(R(0), ADD(VARG(R(0)), U32(I(1))));
case /*ADD.A SRR*/ 0x30: return SETG(R(0), ADD(VARG(R(0)), VARG(R(1))));
case /*SUB.A SC*/ 0x20: return SETG("a10", SUB(VARG("a10"), U32(I(0))));
case /*SUB.A SC*/ 0x20: return SETG(R(0), SUB(VARG(R(0)), U32(I(1))));
default:
if (extract32(ctx->word, 0, 6) == 0x10) {
/*ADDSC.A SRRS*/
return SETG(R(0), ADD(VARG(R(1)), SHL0(VARG("d15"), I(2))));
return SETG(R(0), ADD(VARG(R(1)), SHL0(VARG(R(2)), I(3))));
}
break;
}
Expand All @@ -3534,7 +3507,7 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
}
break;
}
case 0xda: return SETG("d15", U32(I(0)));
case 0xda: return SETG(R(0), U32(I(1)));
case 0x82: return SETG(R(0), sign_ext32_bv(I(1), 4));
case 0xd2: return SETG(R(0), sign_ext64_bv(I(1), 4));
case 0x02: return SETG(R(0), VARG(R(1)));
Expand Down Expand Up @@ -3712,10 +3685,10 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
default: break;
}
break;
case /*LT(SRC)*/ 0xfa: return SETG("d15", BOOL_TO_BV32(SLT(VARG(R(0)), sign_ext32_bv(I(1), 4))));
case /*LT(SRR)*/ 0x7a: return SETG("d15", BOOL_TO_BV32(SLT(VARG(R(0)), VARG(R(1)))));
case /*EQ(SRC)*/ 0xba: return SETG("d15", BOOL_TO_BV32(EQ(VARG(R(0)), sign_ext32_bv(I(1), 4))));
case /*EQ(SRR)*/ 0x3a: return SETG("d15", BOOL_TO_BV32(EQ(VARG(R(0)), VARG(R(1)))));
case /*LT(SRC)*/ 0xfa: return SETG(R(0), BOOL_TO_BV32(SLT(VARG(R(1)), sign_ext32_bv(I(2), 4))));
case /*LT(SRR)*/ 0x7a: return SETG(R(0), BOOL_TO_BV32(SLT(VARG(R(1)), VARG(R(2)))));
case /*EQ(SRC)*/ 0xba: return SETG(R(0), BOOL_TO_BV32(EQ(VARG(R(1)), sign_ext32_bv(I(2), 4))));
case /*EQ(SRR)*/ 0x3a: return SETG(R(0), BOOL_TO_BV32(EQ(VARG(R(1)), VARG(R(2)))));
case /*RSUB(SR)*/ 0x08: SETG(R(0), SUB(S32(0), VARG(R(1))));
default: break;
}
Expand Down Expand Up @@ -3960,10 +3933,10 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_CMOVN:
case TRICORE_INS_CMOV: {
switch (OPC1) {
case 0xaa: return SETG(R(0), ITE(NON_ZERO(VARG("d15")), sign_ext32_bv(I(1), 4), VARG(R(0))));
case 0x2a: return SETG(R(0), ITE(NON_ZERO(VARG("d15")), VARG(R(1)), VARG(R(0))));
case 0xea: return SETG(R(0), ITE(IS_ZERO(VARG("d15")), sign_ext32_bv(I(1), 4), VARG(R(0))));
case 0x6a: return SETG(R(0), ITE(IS_ZERO(VARG("d15")), VARG(R(1)), VARG(R(0))));
case 0xaa: return SETG(R(0), ITE(NON_ZERO(VARG(R(1))), sign_ext32_bv(I(2), 4), VARG(R(0))));
case 0x2a: return SETG(R(0), ITE(NON_ZERO(VARG(R(1))), VARG(R(2)), VARG(R(0))));
case 0xea: return SETG(R(0), ITE(IS_ZERO(VARG(R(1))), sign_ext32_bv(I(2), 4), VARG(R(0))));
case 0x6a: return SETG(R(0), ITE(IS_ZERO(VARG(R(1))), VARG(R(2)), VARG(R(0))));
default: break;
}
break;
Expand Down Expand Up @@ -4275,8 +4248,8 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
break;
// SUB
case 0xa2: return packed_op2_sov(R(0), VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_sub, NULL);
case 0x52: return packed_op2_sov(R(0), VARG("d15"), VARG(R(1)), Word_b, rz_il_op_new_sub, NULL);
case 0x5a: return packed_op2_sov("d15", VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_sub, NULL);
case 0x52:
case 0x5a: return packed_op2_sov(R(0), VARG(R(1)), VARG(R(2)), Word_b, rz_il_op_new_sub, NULL);
case 0x01:
switch (extract32(ctx->word, 20, 8)) {
// SUB.A
Expand All @@ -4285,7 +4258,7 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
}
break;
// SUB.A
case 0x20: return packed_op2_s("a10", VARG("a10"), VARG(R(0)), Word_b, rz_il_op_new_sub, NULL, false);
case 0x20: return packed_op2_s(R(0), VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_sub, NULL, false);
// SUBS
case 0x62: return packed_op2_sov(R(0), VARG(R(0)), VARG(R(1)), Word_b, rz_il_op_new_sub, ssov);
default: break;
Expand Down Expand Up @@ -4672,10 +4645,10 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
}
break;
}
case /*AND(SC)*/ 0x16: return e_op2("d15", VARG("d15"), U32(I(0)), rz_il_op_new_log_and);
case /*AND(SC)*/ 0x16: return e_op2(R(0), VARG(R(0)), U32(I(1)), rz_il_op_new_log_and);
case /*AND(SRR)*/ 0x26: return e_op2(R(0), VARG(R(0)), VARG(R(1)), rz_il_op_new_log_and);
case /*NOT(SR)*/ 0x46: return SETG(R(0), LOGNOT(VARG(R(0))));
case /*OR(SC)*/ 0x96: return e_op2("d15", VARG("d15"), U32(I(0)), rz_il_op_new_log_or);
case /*OR(SC)*/ 0x96: return e_op2(R(0), VARG(R(0)), U32(I(1)), rz_il_op_new_log_or);
case /*OR(SRR)*/ 0xa6: return e_op2(R(0), VARG(R(0)), VARG(R(1)), rz_il_op_new_log_or);
case /*XOR(SRR)*/ 0xc6: return e_op2(R(0), VARG(R(0)), VARG(R(1)), rz_il_op_new_log_xor);
default: break;
Expand Down
10 changes: 4 additions & 6 deletions test/db/analysis/tricore
View file
Original file line number Diff line number Diff line change
Expand Up @@ -540,7 +540,7 @@ EXPECT=<<EOF
| 0x800843a4 ld.w d15, [a14]#-0x64
| 0x800843a8 mov d3, d2
| 0x800843aa mov.a a15, d15
| 0x800843ac st.w [a15]#0x14, d3 ; 20
| 0x800843ac st.w [a15]#0x14, d3
| 0x800843ae ld.w d15, [a14]#-0x64
| 0x800843b2 mov.a a15, d15
| 0x800843b4 ld.w d15, [a15]#4
Expand Down Expand Up @@ -642,7 +642,7 @@ EXPECT=<<EOF
| || `-> 0x800844ca ld.w d15, [a14]#-0x64
| || 0x800844ce mov d2, #0
| || 0x800844d0 mov.a a15, d15
| || 0x800844d2 st.b [a15]#0xc, d2 ; 12
| || 0x800844d2 st.b [a15]#0xc, d2
| || ; CODE XREFS from fcn.800842f0 @ 0x800843de, 0x800844c8
\ ``---> 0x800844d4 ret
EOF
Expand Down Expand Up @@ -893,12 +893,10 @@ EXPECT=<<EOF
| ; SFtype __truncdfsf2(DFtype arg_a) | |
| call dbg.__truncdfsf2 | |
| mov d15, d2 | |
| ; 12 | |
| st.w [a15]#0xc, d15 | |
| ld.a a15, [a14]#-0x18 | |
| ld.a a15, [a15]#0 | |
| ld.w d15, [a14]#-0x14 | |
| ; 16 | |
| st.w [a15]#0x10, d15 | |
| mov d15, #1 | |
`-------------------------------------------------------------' |
Expand Down Expand Up @@ -974,11 +972,11 @@ EXPECT=<<EOF
| 0x80000532 ld.d e4, [a14]#-0x10
| 0x80000536 call dbg.__truncdfsf2 ; SFtype __truncdfsf2(DFtype arg_a)
| 0x8000053a mov d15, d2
| 0x8000053c st.w [a15]#0xc, d15 ; 12
| 0x8000053c st.w [a15]#0xc, d15
| 0x8000053e ld.a a15, [a14]#-0x18
| 0x80000542 ld.a a15, [a15]#0
| 0x80000544 ld.w d15, [a14]#-0x14
| 0x80000548 st.w [a15]#0x10, d15 ; 16
| 0x80000548 st.w [a15]#0x10, d15
| 0x8000054a mov d15, #1
| ----------- true: 0x8000054c
| ; CODE XREF from sym.fn1 @ 0x800004f4
Expand Down
Loading

0 comments on commit 8d0e5a7

Please sign in to comment.