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Implement async traits for peripherals #30

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2 changes: 2 additions & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,11 @@ embedded-hal = { version = "0.2.3", features = ["unproven"] }
nb = "0.1.2"
riscv = "0.5.4"
e310x = { version = "0.8.0", features = ["rt"] }
async-embedded-traits = { version = "0.1.1", optional = true }

[features]
g002 = ["e310x/g002"]
async-traits = ["async-embedded-traits"]

[package.metadata.docs.rs]
features = ["g002"]
43 changes: 43 additions & 0 deletions src/delay.rs
Original file line number Diff line number Diff line change
Expand Up @@ -98,3 +98,46 @@ impl DelayMs<u8> for Sleep {
self.delay_ms(u32::from(ms));
}
}

#[cfg(feature = "async-traits")]
mod async_impls {
use core::future::Future;
use core::pin::Pin;
use core::task::{Context, Poll};
use async_embedded_traits::delay::AsyncDelayMs;
use async_embedded_traits::impl_delay_ms_for_ms_u32;
use super::{Delay, MTIME};

impl AsyncDelayMs<u32> for Delay {
type DelayFuture<'f> = MtimeDelayFuture;

fn async_delay_ms(&mut self, ms: u32) -> Self::DelayFuture<'_> {
let ticks = (ms as u64) * 32768 / 1000;
let mtime = MTIME;
let deadline = mtime.mtime().wrapping_add(ticks);
MtimeDelayFuture {
deadline,
}
}
}

impl_delay_ms_for_ms_u32!(Delay);

pub struct MtimeDelayFuture {
deadline: u64,
}

impl Future for MtimeDelayFuture {
type Output = ();

fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
let mtime = MTIME;
if mtime.mtime() < self.deadline {
cx.waker().wake_by_ref();
Poll::Pending
} else {
Poll::Ready(())
}
}
}
}
3 changes: 3 additions & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,9 @@
#![deny(missing_docs)]
#![no_std]

#![allow(incomplete_features)]
#![cfg_attr(feature = "async-traits", feature(generic_associated_types))]

pub use e310x;

pub mod core;
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2 changes: 2 additions & 0 deletions src/prelude.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,8 @@ pub use embedded_hal::digital::v2::{
StatefulOutputPin as _embedded_hal_digital_v2_StatefulOutputPin,
ToggleableOutputPin as _embedded_hal_digital_v2_ToggleableOutputPin,
};
#[cfg(feature = "async-traits")]
pub use async_embedded_traits::prelude::*;
pub use crate::clock::PrciExt as _e310x_hal_clock_PrciExt;
pub use crate::clock::AonExt as _e310x_hal_clock_AonExt;
pub use crate::gpio::GpioExt as _e310x_hal_gpio_GpioExt;
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218 changes: 218 additions & 0 deletions src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,224 @@ impl<UART: UartX> serial::Write<u8> for Tx<UART> {
}
}

#[cfg(feature = "async-traits")]
mod async_impls {
use core::convert::Infallible;
use core::future::Future;
use core::pin::Pin;
use core::task::{Context, Poll};
use async_embedded_traits::serial::{AsyncRead, AsyncWrite};
use super::{UartX, Serial, Rx, Tx, uart0::RegisterBlock};

impl<UART: UartX + 'static, PINS> AsyncRead for Serial<UART, PINS> {
type Error = Infallible;
type ReadByteFuture<'f> = AsyncReadByteFuture<'f>;
type ReadFuture<'f> = AsyncReadFuture<'f>;

fn async_read_byte(&mut self) -> Self::ReadByteFuture<'_> {
AsyncReadByteFuture {
uart: &self.uart,
}
}

fn async_read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'_> {
AsyncReadFuture {
uart: &self.uart,
data,
offset: 0
}
}
}

impl<UART: UartX + 'static> AsyncRead for Rx<UART> {
type Error = Infallible;
type ReadByteFuture<'f> = AsyncReadByteFuture<'f>;
type ReadFuture<'f> = AsyncReadFuture<'f>;

fn async_read_byte(&mut self) -> Self::ReadByteFuture<'_> {
AsyncReadByteFuture {
uart: &self.uart,
}
}

fn async_read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'_> {
AsyncReadFuture {
uart: &self.uart,
data,
offset: 0
}
}
}

pub struct AsyncReadByteFuture<'a> {
uart: &'a RegisterBlock,
}

impl<'a> Future for AsyncReadByteFuture<'a> {
type Output = Result<u8, Infallible>;

fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
let rxdata = self.uart.rxdata.read();

if rxdata.empty().bit_is_set() {
// TODO: replace with something useful
cx.waker().wake_by_ref();
Poll::Pending
} else {
let byte = rxdata.data().bits() as u8;
Poll::Ready(Ok(byte))
}
}
}

pub struct AsyncReadFuture<'a> {
uart: &'a RegisterBlock,
data: &'a mut [u8],
offset: usize,
}

impl<'a> Future for AsyncReadFuture<'a> {
type Output = Result<(), Infallible>;

fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
while self.offset < self.data.len() {
let rxdata = self.uart.rxdata.read();

if rxdata.empty().bit_is_set() {
// TODO: replace with something useful
cx.waker().wake_by_ref();
return Poll::Pending
} else {
let byte = rxdata.data().bits() as u8;
let offset = self.offset; // Stupid Rust
self.data[offset] = byte;
self.offset += 1;
}
}
Poll::Ready(Ok(()))
}
}

impl<UART: UartX + 'static, PINS> AsyncWrite for Serial<UART, PINS> {
type Error = Infallible;
type WriteByteFuture<'t> = AsyncWriteByteFuture<'t>;
type WriteFuture<'t> = AsyncWriteFuture<'t>;
type FlushFuture<'t> = AsyncFlushFuture<'t>;

fn async_write_byte(&mut self, byte: u8) -> Self::WriteByteFuture<'_> {
AsyncWriteByteFuture {
uart: &self.uart,
byte
}
}

fn async_write<'a>(&'a mut self, data: &'a [u8]) -> AsyncWriteFuture<'a> {
AsyncWriteFuture {
uart: &self.uart,
data,
}
}

fn async_flush(&mut self) -> AsyncFlushFuture<'_> {
AsyncFlushFuture {
uart: &self.uart,
}
}
}

impl<UART: UartX + 'static> AsyncWrite for Tx<UART> {
type Error = Infallible;
type WriteByteFuture<'t> = AsyncWriteByteFuture<'t>;
type WriteFuture<'t> = AsyncWriteFuture<'t>;
type FlushFuture<'t> = AsyncFlushFuture<'t>;

fn async_write_byte(&mut self, byte: u8) -> Self::WriteByteFuture<'_> {
AsyncWriteByteFuture {
uart: &self.uart,
byte
}
}

fn async_write<'a>(&'a mut self, data: &'a [u8]) -> AsyncWriteFuture<'a> {
AsyncWriteFuture {
uart: &self.uart,
data,
}
}

fn async_flush(&mut self) -> AsyncFlushFuture<'_> {
AsyncFlushFuture {
uart: &self.uart,
}
}
}

pub struct AsyncWriteByteFuture<'a> {
uart: &'a RegisterBlock,
byte: u8,
}

impl<'a> Future for AsyncWriteByteFuture<'a> {
type Output = Result<(), Infallible>;

fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
let txdata = self.uart.txdata.read();

if txdata.full().bit_is_set() {
cx.waker().wake_by_ref();
Poll::Pending
} else {
unsafe {
self.uart.txdata.write(|w| w.data().bits(self.byte));
}
Poll::Ready(Ok(()))
}
}
}

pub struct AsyncWriteFuture<'a> {
uart: &'a RegisterBlock,
data: &'a [u8],
}

impl<'a> Future for AsyncWriteFuture<'a> {
type Output = Result<(), Infallible>;

fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
while let Some(byte) = self.data.first() {
let txdata = self.uart.txdata.read();

if txdata.full().bit_is_set() {
cx.waker().wake_by_ref();
return Poll::Pending;
} else {
self.uart.txdata.write(|w| unsafe { w.data().bits(*byte) });
self.data = &self.data[1..];
}
}
Poll::Ready(Ok(()))
}
}

pub struct AsyncFlushFuture<'a> {
uart: &'a RegisterBlock,
}

impl<'a> Future for AsyncFlushFuture<'a> {
type Output = Result<(), Infallible>;

fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
if self.uart.ip.read().txwm().bit_is_set() {
// FIFO count is below the receive watermark (1)
Poll::Ready(Ok(()))
} else {
cx.waker().wake_by_ref();
Poll::Pending
}
}
}
}

// Backward compatibility
impl<TX, RX> Serial<UART0, (TX, RX)> {
/// Configures a UART peripheral to provide serial communication
Expand Down
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