Merge pull request #1209 from en-sc/en-sc/riscv-info-mtopx

target/riscv: drop `mtopi_readable/mtopei_readable` `riscv_info` fields
riscv-collab · Feb 17, 2025 · e1fe15f · e1fe15f
2 parents dd72250 + 06e673e
commit e1fe15f
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Showing 4 changed files with 24 additions and 47 deletions.
diff --git a/src/target/riscv/riscv-011_reg.c b/src/target/riscv/riscv-011_reg.c
@@ -48,10 +48,6 @@ int riscv011_reg_init_all(struct target *target)
 	RISCV_INFO(r);
 	assert(!r->vlenb
 			&& "VLENB discovery is not supported on RISC-V 0.11 targets");
-	assert(!r->mtopi_readable
-			&& "MTOPI discovery is not supported on RISC-V 0.11 targets");
-	assert(!r->mtopei_readable
-			&& "MTOPEI discovery is not supported on RISC-V 0.11 targets");
 	/* Existence of some registers depends on others.
 	 * E.g. the presence of "v0-31" registers is infered from "vlenb" being
 	 * non-zero.

diff --git a/src/target/riscv/riscv-013_reg.c b/src/target/riscv/riscv-013_reg.c
@@ -266,12 +266,7 @@ static int examine_misa(struct target *target)
 
 static int examine_mtopi(struct target *target)
 {
-	RISCV_INFO(r);
-
 	/* Assume the registers exist */
-	r->mtopi_readable = true;
-	r->mtopei_readable = true;
-
 	int res = assume_reg_exist(target, GDB_REGNO_MTOPI);
 	if (res != ERROR_OK)
 		return res;
@@ -281,19 +276,17 @@ static int examine_mtopi(struct target *target)
 
 	riscv_reg_t value;
 	if (riscv_reg_get(target, &value, GDB_REGNO_MTOPI) != ERROR_OK) {
-		r->mtopi_readable = false;
-		r->mtopei_readable = false;
-	} else if (riscv_reg_get(target, &value, GDB_REGNO_MTOPEI) != ERROR_OK) {
+		res = riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPI, false);
+		if (res != ERROR_OK)
+			return res;
+		return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, false);
+	}
+	if (riscv_reg_get(target, &value, GDB_REGNO_MTOPEI) != ERROR_OK) {
 		LOG_TARGET_INFO(target, "S?aia detected without IMSIC");
-		r->mtopei_readable = false;
-	} else {
-		LOG_TARGET_INFO(target, "S?aia detected with IMSIC");
+		return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, false);
 	}
-	res = riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPI, r->mtopi_readable);
-	if (res != ERROR_OK)
-		return res;
-
-	return riscv_reg_impl_set_exist(target, GDB_REGNO_MTOPEI, r->mtopei_readable);
+	LOG_TARGET_INFO(target, "S?aia detected with IMSIC");
+	return ERROR_OK;
 }
 
 /**

diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
@@ -178,15 +178,14 @@ struct riscv_info {
 
 	/* It's possible that each core has a different supported ISA set. */
 	int xlen;
+	/* TODO: use the value from the register cache instead. */
 	riscv_reg_t misa;
-	/* Cached value of vlenb. 0 indicates there is no vector support.
+	/* TODO: use the value from the register cache instead.
+	 * Cached value of vlenb. 0 indicates there is no vector support.
 	 * Note that you can have vector support without misa.V set, because
 	 * Zve* extensions implement vector registers without setting misa.V. */
 	unsigned int vlenb;
 
-	bool mtopi_readable;
-	bool mtopei_readable;
-
 	/* The number of triggers per hart. */
 	unsigned int trigger_count;
 

diff --git a/src/target/riscv/riscv_reg.c b/src/target/riscv/riscv_reg.c
@@ -346,22 +346,11 @@ static bool vlenb_exists(const struct target *target)
 	return riscv_vlenb(target) != 0;
 }
 
-static bool mtopi_exists(const struct target *target)
+static bool reg_exists(const struct target *target, uint32_t regno)
 {
-	RISCV_INFO(info)
-	/* TODO: The naming is quite unfortunate here. `mtopi_readable` refers
-	 * to how the fact that `mtopi` exists was deduced during examine.
-	 */
-	return info->mtopi_readable;
-}
-
-static bool mtopei_exists(const struct target *target)
-{
-	RISCV_INFO(info)
-	/* TODO: The naming is quite unfortunate here. `mtopei_readable` refers
-	 * to how the fact that `mtopei` exists was deduced during examine.
-	 */
-	return info->mtopei_readable;
+	const struct reg * const reg = riscv_reg_impl_cache_entry(target, regno);
+	assert(riscv_reg_impl_is_initialized(reg));
+	return reg->exist;
 }
 
 static bool is_known_standard_csr(unsigned int csr_num)
@@ -508,25 +497,25 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
 		case CSR_MVIP:
 		case CSR_MIEH:
 		case CSR_MIPH:
-			return mtopi_exists(target);
+			return reg_exists(target, GDB_REGNO_MTOPI);
 		case CSR_MIDELEGH:
 		case CSR_MVIENH:
 		case CSR_MVIPH:
-			return mtopi_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPI) &&
 				riscv_xlen(target) == 32 &&
 				riscv_supports_extension(target, 'S');
 			/* Interrupts S-Mode CSRs. */
 		case CSR_SISELECT:
 		case CSR_SIREG:
 		case CSR_STOPI:
-			return mtopi_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPI) &&
 				riscv_supports_extension(target, 'S');
 		case CSR_STOPEI:
-			return mtopei_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPEI) &&
 				riscv_supports_extension(target, 'S');
 		case CSR_SIEH:
 		case CSR_SIPH:
-			return mtopi_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPI) &&
 				riscv_xlen(target) == 32 &&
 				riscv_supports_extension(target, 'S');
 			/* Interrupts Hypervisor and VS CSRs. */
@@ -537,10 +526,10 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
 		case CSR_VSISELECT:
 		case CSR_VSIREG:
 		case CSR_VSTOPI:
-			return mtopi_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPI) &&
 				riscv_supports_extension(target, 'H');
 		case CSR_VSTOPEI:
-			return mtopei_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPEI) &&
 				riscv_supports_extension(target, 'H');
 		case CSR_HIDELEGH:
 		case CSR_HVIENH:
@@ -549,7 +538,7 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
 		case CSR_HVIPRIO2H:
 		case CSR_VSIEH:
 		case CSR_VSIPH:
-			return mtopi_exists(target) &&
+			return reg_exists(target, GDB_REGNO_MTOPI) &&
 				riscv_xlen(target) == 32 &&
 				riscv_supports_extension(target, 'H');
 	}