Merge pull request #1217 from sobuch/not_cachable_mcause_mstatus

target/riscv: dont set mcause and mstatus as cachable
riscv-collab · Jan 31, 2025 · 8f59570 · 8f59570
2 parents 9d431c3 + 94d739a
commit 8f59570
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h
@@ -204,9 +204,7 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
 		case GDB_REGNO_MISA:
 		case GDB_REGNO_DCSR:
 		case GDB_REGNO_DSCRATCH0:
-		case GDB_REGNO_MSTATUS:
 		case GDB_REGNO_MEPC:
-		case GDB_REGNO_MCAUSE:
 		case GDB_REGNO_SATP:
 			/*
 			 * WARL registers might not contain the value we just wrote, but