Support Avalon-MM protocol

lib/rggen/veryl.rb

@@ -28,6 +28,7 @@
     'veryl/register_block/protocol',
     'veryl/register_block/protocol/apb',
     'veryl/register_block/protocol/axi4lite',
+    'veryl/register_block/protocol/avalon',
     'veryl/register_block/protocol/wishbone',
     'veryl/register_block/protocol/native',
     'veryl/register_file/veryl_top',

lib/rggen/veryl/register_block/protocol/avalon.erb

@@ -0,0 +1,17 @@
+inst u_adapter: rggen::rggen_avalon_adapter #(
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  avalon_if:    <%= avalon_if %>,
+  register_if:  <%= register_block.register_if %>
+);

lib/rggen/veryl/register_block/protocol/avalon.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  veryl do
+    build do
+      modport :avalon_if, {
+        name: 'avalon_if',
+        interface_type: 'rggen::rggen_avalon_if', modport: 'agent'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

lib/rggen/veryl/register_block/protocol/native.erb

@@ -7,6 +7,7 @@ inst u_adapter: rggen::rggen_native_adapter #(
   PRE_DECODE:           <%= pre_decode %>,
   BASE_ADDRESS:         <%= base_address %>,
   BYTE_SIZE:            <%= byte_size %>,
+  USE_READ_STROBE:      <%= use_read_strobe %>,
   ERROR_STATUS:         <%= error_status %>,
   DEFAULT_READ_DATA:    <%= default_read_data %>,
   INSERT_SLICER:        <%= insert_slicer %>

lib/rggen/veryl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@
       param :strobe_width, {
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       }
+      param :use_read_strobe, {
+        name: 'USE_READ_STROBE', type: :bit, default: 0
+      }
       modport :csrbus_if, {
         name: 'csrbus_if',
         interface_type: 'rggen::rggen_bus_if', modport: 'slave'

spec/rggen/veryl/register_block/protocol/avalon_spec.rb

@@ -0,0 +1,73 @@
+#! frozen_string_literal: true
+
+RSpec.describe 'register_block/protocol/avalon' do
+  include_context 'veryl common'
+  include_context 'clean-up builder'
+
+  before(:all) do
+    RgGen.enable(:global, [:address_width, :enable_wide_register])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
+    RgGen.enable(:register_block, :protocol, [:avalon])
+    RgGen.enable(:register, [:name, :offset_address, :size, :type])
+    RgGen.enable(:register, :type, [:external])
+    RgGen.enable(:register_block, [:veryl_top])
+  end
+
+  let(:address_width) do
+    16
+  end
+
+  let(:bus_width) do
+    32
+  end
+
+  let(:register_block) do
+    create_register_block do
+      name 'block_0'
+      byte_size 256
+      register { name 'register_0'; offset_address 0x00; size [1]; type :external }
+      register { name 'register_1'; offset_address 0x10; size [1]; type :external }
+      register { name 'register_2'; offset_address 0x20; size [1]; type :external }
+    end
+  end
+
+  def create_register_block(&)
+    configuration =
+      create_configuration(
+        address_width:, bus_width:, protocol: :avalon
+      )
+    create_veryl(configuration, &).register_blocks.first
+  end
+
+  it 'modport #avalon_ifを持つ' do
+    expect(register_block)
+      .to have_modport(
+        :avalon_if,
+        name: 'avalon_if', interface_type: 'rggen::rggen_avalon_if', modport: 'agent'
+      )
+  end
+
+  describe '#generate_code' do
+    it 'rggen_avalon_adapterをインスタンスするコードを生成する' do
+      expect(register_block).to generate_code(:register_block, :top_down, <<~'VERYL')
+        inst u_adapter: rggen::rggen_avalon_adapter #(
+          ADDRESS_WIDTH:        ADDRESS_WIDTH,
+          LOCAL_ADDRESS_WIDTH:  8,
+          BUS_WIDTH:            32,
+          REGISTERS:            3,
+          PRE_DECODE:           PRE_DECODE,
+          BASE_ADDRESS:         BASE_ADDRESS,
+          BYTE_SIZE:            256,
+          ERROR_STATUS:         ERROR_STATUS,
+          DEFAULT_READ_DATA:    DEFAULT_READ_DATA,
+          INSERT_SLICER:        INSERT_SLICER
+        )(
+          i_clk:        i_clk,
+          i_rst:        i_rst,
+          avalon_if:    avalon_if,
+          register_if:  register_if
+        );
+      VERYL
+    end
+  end
+end

spec/rggen/veryl/register_block/protocol/native_spec.rb

@@ -39,12 +39,17 @@ def create_register_block(&)
     create_veryl(configuration, &).register_blocks.first
   end
 
-  it 'パラメータ#strobe_widthを持つ' do
+  it 'パラメータ#strobe_width/#use_read_strobeを持つ' do
     expect(register_block)
       .to have_param(
         :strobe_width,
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       )
+    expect(register_block)
+      .to have_param(
+        :use_read_strobe,
+        name: 'USE_READ_STROBE', type: :bit, default: 0
+      )
   end
 
   it 'modport #csrbus_ifを持つ' do
@@ -67,6 +72,7 @@ def create_register_block(&)
           PRE_DECODE:           PRE_DECODE,
           BASE_ADDRESS:         BASE_ADDRESS,
           BYTE_SIZE:            256,
+          USE_READ_STROBE:      USE_READ_STROBE,
           ERROR_STATUS:         ERROR_STATUS,
           DEFAULT_READ_DATA:    DEFAULT_READ_DATA,
           INSERT_SLICER:        INSERT_SLICER