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retpolanne · Dec 15, 2023 · 32178ef · 32178ef
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diff --git a/_posts/2023-12-12-PHYnal-fix.markdown b/_posts/2023-12-12-PHYnal-fix.markdown
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+---
+layout: post
+title: "Orange Pi PHYnal Fix"
+date: 2023-12-12 08:53:16 -0300
+categories: embedded
+tags: orangepi phy
+---
+
+I decided to get back into fixing the Orange Pi One Plus ethernet. 
+
+My workflow is as follows: 
+
+```sh
+devtool modify virtual/kernel
+devtool build linux-mainline
+bitbake core-image-minimal
+bmaptool copy --bmap orange-pi-one-plus/tmp/deploy/images/orange-pi-one-plus/core-image-minimal-orange-pi-one-plus.rootfs.wic.bmap orange-pi-one-plus/tmp/deploy/images/orange-pi-one-plus/core-image-minimal-orange-pi-one-plus.rootfs.wic.gz /tmp/opi
+```
+
+I removed this change [1] from meta-sunxi so that u-boot reports no ethernet and add the line
+
+```
+CORE_IMAGE_EXTRA_INSTALL += " kernel-modules"
+```
+
+So that the `dwmac-sun8i` kernel module starts. 
+
+Without my change:
+
+```
+Configuring network interfaces... [    5.992589] dwmac-sun8i 5020000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
+[    6.000823] dwmac-sun8i 5020000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19)
+
+ifconfig
+lo        Link encap:Local Loopback  
+          inet addr:127.0.0.1  Mask:255.0.0.0
+          UP LOOPBACK RUNNING  MTU:65536  Metric:1
+          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
+          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
+          collisions:0 txqueuelen:1000 
+          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
+```
+
+The ethernet LED blinks, but there's not PHY attached to it. 
+
+It's also important to note that I reverted changes in U-boot, so there's no early ethernet :)
+
+```
+Net:   No ethernet found.
+```
+
+After my changes:
+
+```
+Configuring network interfaces... [    6.060020] dwmac-sun8i 5020000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
+[    6.069460] dwmac-sun8i 5020000.ethernet eth0: PHY [stmmac-0:01] driver [RTL8211E Gigabit Ethernet] (irq=POLL)
+[    6.079547] dwmac-sun8i 5020000.ethernet eth0: No Safety Features support found
+[    6.086879] dwmac-sun8i 5020000.ethernet eth0: No MAC Management Counters available
+[    6.094553] dwmac-sun8i 5020000.ethernet eth0: PTP not supported by HW
+[    6.101594] dwmac-sun8i 5020000.ethernet eth0: configuring for phy/rgmii-id link mode
+```
+
+## Formatting patch and sending email
+
+```sh
+git format-patch HEAD~1
+./scripts/checkpatch.pl 0001-ARM64-dts-sunxi-Add-compatible-properties-to-Realtek.patch
+# Send to myself
+git send-email --to "Anne Macedo <[email protected]>" 0001-arm64-dts-allwinner-Orange-Pi-One-Plus-PHY-support.patch
+```
+
+## Lessons learned on PHYs and voltage regulators
+
+Andre Przywara, who reviewed my patch, kindly explained a whole lot of things that I'm going to include on the next posts. See ya!
+
+## References
+
+\[1] [add u-boot ethernet support to orange pi one plus (h6) #389](https://github.com/linux-sunxi/meta-sunxi/pull/389/files)
diff --git a/_posts/2023-12-15-PHYnal-explanation.markdown b/_posts/2023-12-15-PHYnal-explanation.markdown
@@ -0,0 +1,43 @@
+---
+layout: post
+title: "Orange Pi One Plus PHYnal Explanation"
+date: 2023-12-15 18:58:45 -0300
+categories: embedded-systems
+tags: kernel-dev
+---
+
+After I've submitted the patch for the Orange Pi One Plus PHY, Andre Przywara made a few comments which were very insightful. The thread is in [1]
+
+## Metal
+
+According to Andre, Orange Pi One Plus uses two regulators for Ethernet: 3.3V (powered by the PMIC's ALDO2 rail) and a 
+discrete 2.5V regulator, enabled by GPIO PD6, for the voltage level on the MDIO lines. There's also a reset line for the PHY held by a pull-up resistor, that is not described on the device tree.
+
+## What is PHY after all?
+
+Andre also sent me an amazing explanation about what is PHY. 
+
+Let's take TTL - transistor-transistor logic, which we use in UART. 5V-0V logic works well for it, albeit quite slow. Let's imagine a big cable, 2 meters long, connected to the same UART and using the same TTL logic - that won't work, right? So we need PHYs. 
+
+The MAC (which is the Ethernet device inside the SoC, in our case the Allwinner H6) generated the signal with correct timing and logic level (2.5V in our case) and PHY does the "linking", it talks to whatever is in the physical layer - fiber, coax, twisted pair copper cable, whatever.
+
+## RGMII
+
+What is MII? According to [2], it's a standard interface to connect Ethernet MAC block to a PHY chip. The standard is IEEE 802.3u (remember that from our DT's mdio node?)
+
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+ 		reg = <1>;
+ 	};
+ };
+
+There's a device called pinmux (pin multiplexer) that defines which signal gets connected to which pin. 
+
+> This post is a work in progress and I'll update it as soon as I get more interesting stuff going on.
+
+## References
+
+\[1] [arm64: dts: allwinner: Orange Pi One Plus PHY support](https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/)
+
+\[2] [Media-independent interface](https://en.wikipedia.org/wiki/Media-independent_interface)
diff --git a/_posts/2023-12-15-rpi-ocd.markdown b/_posts/2023-12-15-rpi-ocd.markdown
@@ -0,0 +1,22 @@
+---
+layout: post
+title: "Raspberry Pi CM4 and OpenOCD"
+date: 2023-12-15 18:02:28 -0300
+categories: kernel-dev
+tags: embedded jtag
+---
+
+I'm trying to debug the Renesas XHCI bug using the Raspberry Pi CM4 (which has a PCI interface). However, it doesn't 
+support IOMMU, so I can't debug using QEMU... I bought a JTAG then and I'm going to use it with OpenOCD :)
+
+## Installing GDB Multiarch on Arch Linux
+
+```sh
+yay -S gdb-multiarch
+```
+
+I've built openocd from the source.
+
+## References
+
+\[1] [https://linaro.atlassian.net/wiki/x/CJzH4wU](https://linaro.atlassian.net/wiki/spaces/TCWGPUB/pages/25296346120/Raspberry+Pi+Linux+kernel+debugging+with+OpenOCD)