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Type abbrevs to abbrev
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lfrenot committed Jan 28, 2025
1 parent 65fe108 commit cad2ca9
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Showing 4 changed files with 8 additions and 8 deletions.
4 changes: 2 additions & 2 deletions src/sail_lean_backend/pretty_print_lean.ml
Original file line number Diff line number Diff line change
Expand Up @@ -529,9 +529,9 @@ let doc_typdef ctx (TD_aux (td, tannot) as full_typdef) =
(* TODO don't ignore type quantifiers *)
nest 2 (flow (break 1) [string "structure"; string id; string "where"] ^^ hardline ^^ enums_doc)
| TD_abbrev (Id_aux (Id id, _), tq, A_aux (A_typ t, _)) ->
nest 2 (flow (break 1) [string "def"; string id; coloneq; doc_typ ctx t])
nest 2 (flow (break 1) [string "abbrev"; string id; coloneq; doc_typ ctx t])
| TD_abbrev (Id_aux (Id id, _), tq, A_aux (A_nexp ne, _)) ->
nest 2 (flow (break 1) [string "def"; string id; colon; string "Int"; coloneq; doc_nexp ctx ne])
nest 2 (flow (break 1) [string "abbrev"; string id; colon; string "Int"; coloneq; doc_nexp ctx ne])
| _ -> failwith ("Type definition " ^ string_of_type_def_con full_typdef ^ " not translatable yet.")

(* Copied from the Coq PP *)
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2 changes: 1 addition & 1 deletion test/lean/bitfield.expected.lean
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ import Out.Sail.Sail

open Sail

def cr_type := (BitVec 8)
abbrev cr_type := (BitVec 8)

inductive Register : Type where
| R
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4 changes: 2 additions & 2 deletions test/lean/register_vector.expected.lean
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ import Out.Sail.Sail

open Sail

def reg_index := Nat
abbrev reg_index := Nat

inductive Register : Type where
| R0
Expand Down Expand Up @@ -41,7 +41,7 @@ inductive Register : Type where
open Register

abbrev RegisterType : Register → Type
| .R0 => (BitVec 64)Reg
| .R0 => (BitVec 64)
| .R1 => (BitVec 64)
| .R2 => (BitVec 64)
| .R3 => (BitVec 64)
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6 changes: 3 additions & 3 deletions test/lean/typedef.expected.lean
Original file line number Diff line number Diff line change
Expand Up @@ -2,11 +2,11 @@ import Out.Sail.Sail

open Sail

def xlen : Int := 64
abbrev xlen : Int := 64

def xlen_bytes : Int := 8
abbrev xlen_bytes : Int := 8

def xlenbits := (BitVec 64)
abbrev xlenbits := (BitVec 64)

/-- Type quantifiers: k_n : Int, m : Int, m ≥ k_n -/
def EXTZ {m : _} (v : (BitVec k_n)) : (BitVec m) :=
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