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commits extracted from sysemu PR #103

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androm3da
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These commits were identified during review as being not strictly related to system emulation.

The BADVA reg is referred to with the wrong identifier.  The
CAUSE reg field of SSR is not yet modeled, we will dump
the SSR in a subsequent commit.

Signed-off-by: Brian Cain <[email protected]>
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".

Signed-off-by: Brian Cain <[email protected]>
@quic-mathbern
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It's odd to have target/hexagon: Fix undetected "multiple writes to same reg" before target/hexagon: raise exception on multiple writes to same reg (a fix before the feat. is implemented?). Perhaps we should reorder or squash those two?

quic-mathbern and others added 3 commits February 12, 2025 12:46
As specified by the PRM, we should raise an exception when a packet
contains multiple writes to the same register. Lets introduce a bitmap
at the CPUArchState, looking for writes to already written registers and
properly generate an exception when needed. Also add a test case to
tests/tcg/system.

The added test shows a scenario in which multiple writes are performed
to the same register but qemu fails to detect that and throw the
appropriated exception. This happens because we are not cleaning
hex_slot_cancelled as frequently as we should, so an old state is used
and the packet that should raise an exception is considered as cancelled
by the code that would detect the multiple writes issue. Let's fix that
by cleaning hex_slot_canceled on all conditional instructions instead,
which should cover all cases where the variable is used to detect
multiple writes.

Signed-off-by: Matheus Tavares Bernardino <[email protected]>
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.

Signed-off-by: Brian Cain <[email protected]>
@androm3da
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It's odd to have target/hexagon: Fix undetected "multiple writes to same reg" before target/hexagon: raise exception on multiple writes to same reg (a fix before the feat. is implemented?). Perhaps we should reorder or squash those two?

squashed, thanks for the suggestion.

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