Align performance counters for CV32E40P

rtos/pmsis/pmsis_api/include/pmsis/chips/default_cv32e40p.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __PMSIS_CHIPS_DEFAULT_H__
+#define __PMSIS_CHIPS_DEFAULT_H__
+
+/**
+ * \ingroup groupChips
+ */
+
+/**
+ * \enum pi_pad_e
+ * \brief Pad numbers.
+ *
+ * This is used to identify pads.
+ */
+typedef enum
+{
+    PI_PAD_NONE
+} pi_pad_e;
+
+/**
+ * \enum pi_gpio_e
+ * \brief GPIO numbers.
+ *
+ * List of available GPIO pins.
+ */
+typedef enum
+{
+    PI_GPIO_NONE
+} pi_gpio_e;
+
+/** \enum pi_perf_event_e
+ * \brief Performance event identifiers.
+ *
+ * This can be used to describe which performance event to monitor (cycles,
+ * cache miss, etc).
+ */
+typedef enum {
+  PI_PERF_CYCLES        = 17, /*!< Total number of cycles (also includes the
+    cycles where the core is sleeping). Be careful that this event is using a
+    timer shared within the cluster, so resetting, starting or stopping it on
+    one core will impact other cores of the same cluster. */
+  PI_PERF_ACTIVE_CYCLES = 0,  /*!< Counts the number of cycles the core was
+    active (not sleeping). */
+  PI_PERF_INSTR         = 1,  /*!< Counts the number of instructions executed.
+  */
+  PI_PERF_LD_STALL      = 2,  /*!< Number of load data hazards. */
+  PI_PERF_JR_STALL      = 3,  /*!< Number of jump register data hazards. */
+  PI_PERF_IMISS         = 4,  /*!< Cycles waiting for instruction fetches, i.e.
+    number of instructions wasted due to non-ideal caching. */
+  PI_PERF_LD            = 5,  /*!< Number of data memory loads executed.
+    Misaligned accesses are counted twice. */
+  PI_PERF_ST            = 6,  /*!< Number of data memory stores executed.
+    Misaligned accesses are counted twice. */
+  PI_PERF_JUMP          = 7,  /*!< Number of unconditional jumps (j, jal, jr,
+    jalr). */
+  PI_PERF_BRANCH        = 8,  /*!< Number of branches. Counts both taken and
+    not taken branches. */
+  PI_PERF_BTAKEN        = 9, /*!< Number of taken branches. */
+  PI_PERF_RVC           = 10, /*!< Number of compressed instructions
+    executed. */
+  PI_PIPE_STALL         = 11, /*!< Number of cycles from stalled pipeline. */
+  PI_APU_TYPE           = 12, /*!< Number of type conflicts on APU/FP. */
+  PI_APU_CONT           = 13, /*!< Number of contentions on APU/FP. */
+  PI_APU_DEP            = 14, /*!< Number of dependency stall on APU/FP. */
+  PI_APU_WB             = 15  /*!< Number of write backs on APU/FP. */
+} pi_perf_event_e;
+
+/**
+ * @}
+ */
+
+#endif  /* __PMSIS_CHIPS_GAP9_PAD_H__ */

rtos/pulpos/common/include/pmsis.h

@@ -14,7 +14,7 @@
  * limitations under the License.
  */
 
-/* 
+/*
  * Authors: Germain Haugou, GreenWaves Technologies ([email protected])
  */
 
@@ -39,6 +39,8 @@
 #elif defined(__GAP9__)
 #include "pmsis/chips/gap9/pad.h"
 #include "pmsis/chips/gap9/gpio.h"
+#elif defined(ARCHI_HAS_COREV)
+#include "pmsis/chips/default_cv32e40p.h"
 #else
 #include "pmsis/chips/default.h"
 #endif
@@ -76,4 +78,3 @@
 #include <pos/implem/implem.h>
 
 #endif
-

rtos/pulpos/common/include/pos/implem/perf.h

@@ -37,15 +37,23 @@ static inline void pi_perf_cl_reset()
 {
 #ifdef ARCHI_HAS_CLUSTER
   timer_reset(timer_base_cl(0, 0, 0));
+  #ifndef ARCHI_HAS_COREV
   cpu_perf_setall(0);
+  #else
+  cpu_perf_setall(MCOUNTINHIBIT_RESET); // 0xFFFF_FFFD resets performance counters in cv32e40p (mcountinhibit, processor specs pag. 43)
+  #endif
 #endif
 }
 
 static inline void pi_perf_fc_reset()
 {
 #ifdef ARCHI_HAS_FC
   timer_reset(timer_base_fc(0, 0));
+  #ifndef ARCHI_HAS_COREV
   cpu_perf_setall(0);
+  #else
+  cpu_perf_setall(MCOUNTINHIBIT_RESET); // 0xFFFF_FFFD resets performance counters in cv32e40p (mcountinhibit, processor specs pag. 43)
+  #endif
 #endif
 }
 
@@ -61,15 +69,23 @@ static inline void pi_perf_cl_start()
 {
 #ifdef ARCHI_HAS_CLUSTER
   timer_start(timer_base_cl(0, 0, 0));
+  #ifndef ARCHI_HAS_COREV
   cpu_perf_conf(PCMR_ACTIVE | PCMR_SATURATE);
+  #else
+  cpu_perf_conf(MCOUNTINHIBIT_ACTIVE);
+  #endif
 #endif
 }
 
 static inline void pi_perf_fc_start()
 {
 #ifdef ARCHI_HAS_FC
   timer_start(timer_base_fc(0, 0));
+  #ifndef ARCHI_HAS_COREV
   cpu_perf_conf(PCMR_ACTIVE | PCMR_SATURATE);
+  #else
+  cpu_perf_conf(MCOUNTINHIBIT_ACTIVE);
+  #endif
 #endif
 }
 
@@ -85,7 +101,11 @@ static inline void pi_perf_cl_stop()
 {
 #ifdef ARCHI_HAS_CLUSTER
   timer_conf_set(timer_base_cl(0, 0, 0), TIMER_CFG_LO_ENABLE(0));
+  #ifndef ARCHI_HAS_COREV
   cpu_perf_conf(0);
+  #else
+  cpu_perf_conf(MCOUNTINHIBIT_RESET);
+  #endif
 #endif
 }
 
@@ -105,6 +125,7 @@ static inline void pi_perf_stop()
     pi_perf_cl_stop();
 }
 
+// get mhpmcounter{4, 31} events count with NUM_MHPMCOUNTERS = 16
 static inline unsigned int pi_perf_cl_read(int event)
 {
 #ifdef ARCHI_HAS_CLUSTER
@@ -114,7 +135,11 @@ static inline unsigned int pi_perf_cl_read(int event)
   }
   else
   {
-    return cpu_perf_get(event);
+#if __PLATFORM__ != ARCHI_PLATFORM_BOARD
+    return cpu_perf_get(1 + event);
+#else
+    return cpu_perf_get(0);
+#endif
   }
 #else
   return 0;
@@ -130,7 +155,11 @@ static inline unsigned int pi_perf_fc_read(int event)
   }
   else
   {
-    return cpu_perf_get(event);
+#if __PLATFORM__ != ARCHI_PLATFORM_BOARD
+    return cpu_perf_get(1 + event);
+#else
+    return cpu_perf_get(0);
+#endif
   }
 #else
   return 0;
@@ -145,6 +174,67 @@ static inline unsigned int pi_perf_read(int event)
     return pi_perf_cl_read(event);
 }
 
+
+#ifdef ARCHI_HAS_COREV
+
+// CV32E40P-specific API functions for handling Performance Counters reads
+
+// Get clock cycle count from mcycle counter
+static inline unsigned int pi_perf_cl_read_mcycle()
+{
+#ifdef ARCHI_HAS_CLUSTER
+  return cpu_perf_get_mcycle();
+#else
+  return 0;
+#endif
+}
+
+static inline unsigned int pi_perf_fc_read_mcycle()
+{
+#ifdef ARCHI_HAS_FC
+  return cpu_perf_get_mcycle();
+#else
+  return 0;
+#endif
+}
+
+static inline unsigned int pi_perf_read_mcycle()
+{
+  if (hal_is_fc())
+    return pi_perf_fc_read_mcycle();
+  else
+    return pi_perf_cl_read_mcycle();
+}
+
+
+// Get instructions count from minstret counter
+static inline unsigned int pi_perf_cl_read_minstret()
+{
+#ifdef ARCHI_HAS_CLUSTER
+  return cpu_perf_get_minstret();
+#else
+  return 0;
+#endif
+}
+
+static inline unsigned int pi_perf_fc_read_minstret()
+{
+#ifdef ARCHI_HAS_FC
+  return cpu_perf_get_minstret();
+#else
+  return 0;
+#endif
+}
+
+static inline unsigned int pi_perf_read_minstret()
+{
+  if (hal_is_fc())
+    return pi_perf_fc_read_minstret();
+  else
+    return pi_perf_cl_read_minstret();
+}
+#endif
+
 #endif
 
 /// @endcond

rtos/pulpos/common/kernel/crt0.S

@@ -21,7 +21,7 @@
 #include "archi/pulp.h"
 
     .section .text_l2
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     .attribute arch, "rv32imc_xcorev2p0"
 #endif
     .global pos_init_entry

rtos/pulpos/common/kernel/irq_asm.S

@@ -20,7 +20,7 @@
 
 
   .section .text_l2
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     .attribute arch, "rv32imc_xcorev2p0"
 #endif
   .global pos_irq_call_external_c_function

rtos/pulpos/common/kernel/soc_event_eu.S

@@ -14,7 +14,7 @@
 # limitations under the License.
 #
 
-# 
+#
 # Authors: Germain Haugou, GreenWaves Technologies ([email protected])
 #
 
@@ -59,7 +59,7 @@ pos_soc_event_handler_asm:
     sw  x9, 0(x10)
 
     # Extract ID part
-    #ifdef ARCHI_HAS_COREV
+    #if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     cv.extractur x10, x8, EU_SOC_EVENTS_EVENT_MASK_BITS-1, EU_SOC_EVENTS_EVENT_MASK_OFFSET
     #else
     p.extractu x10, x8, EU_SOC_EVENTS_EVENT_MASK_BITS-1, EU_SOC_EVENTS_EVENT_MASK_OFFSET
@@ -139,8 +139,7 @@ pos_soc_event_store_asm:
     lw      x12, %tiny(pos_soc_event_status)(x11)
     andi    x10, x10, 0x1f
 
-    #ifdef ARCHI_HAS_COREV
-    cv.bsetr x12, x12, x10
+    #if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))    cv.bsetr x12, x12, x10
     #else
     p.bsetr x12, x12, x10
     #endif

rtos/pulpos/common/kernel/soc_event_v2_itc.S

@@ -14,15 +14,15 @@
 # limitations under the License.
 #
 
-# 
+#
 # Authors: Germain Haugou, GreenWaves Technologies ([email protected])
 #
 
 #include <archi/pulp.h>
 
 
     .section .text_l2
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     .attribute arch, "rv32imc_xcorev2p0"
 #endif
 
@@ -77,13 +77,13 @@
     lw   x11, %tiny(pos_soc_event_callback_arg)(x11)
 #else
     la   t0, pos_soc_event_callback
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     cv.lw x12, t0(x11)
 #else
     p.lw x12, t0(x11)
 #endif /*ARCHI_HAS_COREV*/
     la   t0, pos_soc_event_callback_arg
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     cv.lw x11, t0(x11)
 #else
     p.lw x11, t0(x11)
@@ -112,14 +112,14 @@ pos_soc_event_store_asm:
     lw      x12, %tiny(pos_soc_event_status)(x11)
 #else
     la   t0, pos_soc_event_status
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     cv.lw x12, t0(x11)
 #else
     p.lw x12, t0(x11)
 #endif /*ARCHI_HAS_COREV*/
 #endif
     andi    x10, x10, 0x1f
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     li     x11, 1
     sll    x11, x11, x10
     or     x12, x12, x11
@@ -132,7 +132,7 @@ pos_soc_event_store_asm:
     sw      x12, %tiny(pos_soc_event_status)(x11)
 #else
     la      t0, pos_soc_event_status
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     cv.sw    x12, t0(x11)
 #else
     p.sw    x12, t0(x11)

rtos/pulpos/common/kernel/task_asm.S

@@ -22,7 +22,7 @@
 
     .section .text_l2
 
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     .attribute arch, "rv32imc_xcorev2p0"
 #endif
 

rtos/pulpos/common/kernel/time_asm.S

@@ -22,7 +22,7 @@
 
     .section .text_l2
 
-#ifdef ARCHI_HAS_COREV
+#if defined(ARCHI_HAS_COREV) && (!defined(__PULP_TOOLCHAIN__) && defined(__COREV_TOOLCHAIN__))
     .attribute arch, "rv32imc_xcorev2p0"
 #endif