[hardware] Parametrize DMA for DAS

[software] Add DMA with DAS test

Author: mbertuletti

Bender.yml

@@ -44,7 +44,6 @@ sources:
   # Level 3
   - hardware/src/mempool_group.sv
   # Level 4
-  - hardware/src/idma_partition_midend.sv
   - hardware/src/mempool_cluster.sv
   # Level 5
   - hardware/src/ctrl_registers.sv

config/config.mk

@@ -74,7 +74,7 @@ zquarterinx ?= 0
 xDivSqrt ?= 0
 
 # Enable configurable addressing scheme in the heap
-das ?= 1
+das ?= 0
 num_das_partitions ?= 4
 # Size of DAS-heap per core
 das_mem_size ?= 2048

hardware/deps/idma/Bender.yml

@@ -25,8 +25,6 @@ sources:
   - src/midends/idma_split_midend.sv
   - src/midends/idma_distributed_midend.sv
   # If enabled DAS
-  - src/midends/idma_split_midend_v2.sv
-  - src/midends/idma_distributed_midend_v2.sv
   - src/frontends/mempool/mempool_dma_frontend_reg_pkg.sv
   - src/frontends/mempool/mempool_dma_frontend_reg_top.sv
   - src/frontends/mempool/mempool_dma.sv

hardware/deps/idma/src/midends/idma_address_scrambler.sv

@@ -7,168 +7,91 @@
 // Current constraints:
 
 // Author: Bowen Wang <[email protected]>
+// Author: Marco Bertuletti <[email protected]>
 
 module idma_address_scrambler #(
   parameter int unsigned AddrWidth         = 32,
   parameter int unsigned DataWidth         = 32,
   parameter int unsigned ByteOffset        = 2,
+  parameter bit          Bypass            = 0,
   parameter int unsigned NumTiles          = 128,
   parameter int unsigned NumBanksPerTile   = 32,
-  parameter bit          Bypass            = 0,
-  parameter int unsigned SeqMemSizePerTile = 4*1024,
-  parameter int unsigned HeapSeqMemSizePerTile = 8*2048,
-  parameter int unsigned MemSizePerTile        = 8*4*1024,
-  parameter int unsigned MemSizePerRow         = 4*4*1024,  // 4bytes * 4096 banks
-  parameter int unsigned TCDMSize              = 1024*1024
+  parameter int unsigned TCDMSizePerBank   = 1024,
+  parameter int unsigned NumDASPartitions  = 4,
+  parameter int unsigned MemSizePerTile    = NumBanksPerTile*TCDMSizePerBank,
+  parameter int unsigned MemSizePerRow     = (1 << ByteOffset)*NumBanksPerTile*NumTiles
 ) (
-  input  logic [AddrWidth-1:0]      address_i,
-  input  logic [31:0]               num_bytes_i,
-  input  logic [3:0][7:0]           group_factor_i,
-  // For each allocation, the maximum number of rows assigned can be 128 rows
-  input  logic [3:0][7:0]           allocated_size_i,
-  input  logic [3:0][DataWidth-1:0] start_addr_scheme_i,
-  output logic [7:0]                group_factor_o,
-  output logic [7:0]                allocated_size_o,
-  output logic [AddrWidth-1:0]      address_o
+  input  logic [AddrWidth-1:0]                            address_i,
+  input  logic [31:0]                                     num_bytes_i,
+  input  logic [NumDASPartitions-1:0][$clog2(NumTiles):0] group_factor_i,
+  input  logic [NumDASPartitions-1:0][$clog2(NumTiles):0] allocated_size_i,
+  input  logic [NumDASPartitions-1:0][DataWidth-1:0]      start_addr_scheme_i,
+  output logic [$clog2(NumTiles):0]                       group_factor_o,
+  output logic [$clog2(NumTiles):0]                       allocated_size_o,
+  output logic [AddrWidth-1:0]                            address_o
 );
   // Basic Settings
   localparam int unsigned BankOffsetBits    = $clog2(NumBanksPerTile);
   localparam int unsigned TileIdBits        = $clog2(NumTiles);
   localparam int unsigned ConstantBitsLSB   = ByteOffset + BankOffsetBits;
 
-  // Heap Sequential Settings
-  localparam int unsigned HeapSeqPerTileBits = $clog2(MemSizePerTile);             // log2(8*4096) = 15 | RowIndexBits + ConstBits
-  localparam int unsigned HeapSeqTotalBits   = HeapSeqPerTileBits+TileIdBits;      // 15+7=22           | used for address_o assignment 
-  localparam int unsigned RowIndexBits       = HeapSeqPerTileBits-ConstantBitsLSB; // 15-7=8            | RowIndex
-
   if (Bypass || NumTiles < 2) begin
     assign address_o = address_i;
   end else begin
-    // ------ Heap Sequential Signals ------ //
-    // `shift_index`   : how many bits to shift for TileID bits in each partition
-    // `shift_index_sc`: how many bits need to swap within Row Index 
-    logic [3:0][2:0] shift_index; 
-    logic [3:0][2:0] shift_index_sc;
-    for (genvar i = 0; i < 4; i++) begin : gen_shift_index
-        always_comb begin
-            case(group_factor_i[i])
-                128: shift_index[i] = 7;
-                64:  shift_index[i] = 6;
-                32:  shift_index[i] = 5;
-                16:  shift_index[i] = 4;
-                8:   shift_index[i] = 3;
-                4:   shift_index[i] = 2;
-                2:   shift_index[i] = 1;
-                default: shift_index[i] = 0;
-            endcase
-
-            case(allocated_size_i[i])
-                128: shift_index_sc[i] = 7;
-                64:  shift_index_sc[i] = 6;
-                32:  shift_index_sc[i] = 5;
-                16:  shift_index_sc[i] = 4;
-                8:   shift_index_sc[i] = 3;
-                4:   shift_index_sc[i] = 2;
-                2:   shift_index_sc[i] = 1;
-                default: shift_index_sc[i] = 0;
-            endcase
-        end
-    end
-
-    // post-scramble row index
-    logic [RowIndexBits-1:0]      post_scramble_row_index;
-    logic [TileIdBits-1:0]        post_scramble_tile_id;
-
-    logic [3:0][RowIndexBits-1:0] mask_row_index, mask_row_index_n;
-    logic [3:0][TileIdBits-1:0]   mask_tile_id,   mask_tile_id_n;
 
-    logic [TileIdBits-1:0]        heap_tile_id;
+    // ------ Heap Sequential Signals ------ //
 
-    for (genvar j = 0; j < 4; j++) begin : gen_mask
-      assign mask_row_index[j] = (shift_index_sc[j] == 0) ? {RowIndexBits{1'b0}} : ({RowIndexBits{1'b1}} >> (RowIndexBits-shift_index_sc[j]));
-      assign mask_tile_id[j]   = (shift_index[j] == 0)    ? {TileIdBits{1'b0}}   : ({TileIdBits{1'b1}}   >> (TileIdBits  -shift_index[j]));
-      
-      assign mask_row_index_n[j] = ~mask_row_index[j];
-      assign mask_tile_id_n[j]   = ~mask_tile_id[j];
+    // `tile_index` : how many bits to shift for TileID bits in each partition
+    // `row_index`: how many bits need to swap within Row Index
+    logic [NumDASPartitions-1:0][$clog2($clog2(NumTiles)+1)-1:0] tile_index;
+    logic [NumDASPartitions-1:0][$clog2($clog2(NumTiles)+1)-1:0] row_index;
+
+    for (genvar i = 0; i < NumDASPartitions; i++) begin : gen_shift_index
+      lzc #(
+        .WIDTH ($clog2(NumTiles)+1),
+        .MODE  (1'b0              )
+      ) i_log_tile_index (
+        .in_i    (group_factor_i[i]),
+        .cnt_o   (tile_index[i]    ),
+        .empty_o (/* Unused */     )
+      );
+      lzc #(
+        .WIDTH ($clog2(NumTiles)+1),
+        .MODE  (1'b0            )
+      ) i_log_row_index (
+        .in_i    (allocated_size_i[i][$clog2(NumTiles):0]),
+        .cnt_o   (row_index[i]                           ),
+        .empty_o (/* Unused */                           )
+      );
     end
 
-    assign heap_tile_id = address_i[(TileIdBits+ConstantBitsLSB-1):ConstantBitsLSB];
-
     always_comb begin
+
       // Default: Unscrambled
       address_o = address_i;
       group_factor_o   = '0;
       allocated_size_o = '0;
-      post_scramble_row_index  = 'b0;
-      post_scramble_tile_id    = 'b0;
-      // Need one more logic for interleaved heap region
-      // group_factor_o = {7{1'b1}};
-      // Sequential Heap Region 
+
       // TODO (bowwang): add a new register to indicate the start addr of sequential heap region, currently hard coded
-      // if (address_i < start_addr_scheme_i[0]) begin
       if (address_i < 32'h00120000) begin
-        group_factor_o   = 128; // fully interleaved
-        allocated_size_o = num_bytes_i/(4*4096);
-      end else if ( (address_i >= start_addr_scheme_i[0]) && (address_i < start_addr_scheme_i[0]+MemSizePerRow*allocated_size_i[0]) ) begin
-
-        post_scramble_row_index  = 'b0;
-        post_scramble_tile_id    = 'b0;
-        // 1. `post_scramble_row_index` generation
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + shift_index[0])) & mask_row_index[0];
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + TileIdBits    )) & mask_row_index_n[0];
-
-        // 2. `post_scramble_tile_id` generation
-        post_scramble_tile_id   |= heap_tile_id & mask_tile_id[0];
-        post_scramble_tile_id   |= (address_i >> (ConstantBitsLSB + shift_index_sc[0])) & mask_tile_id_n[0];
-
-        address_o[HeapSeqTotalBits-1:ConstantBitsLSB] = {post_scramble_row_index, post_scramble_tile_id};
-        group_factor_o   = group_factor_i[0];
-        allocated_size_o = allocated_size_i[0];
-      end else if ( (address_i >= start_addr_scheme_i[1]) && (address_i < start_addr_scheme_i[1]+MemSizePerRow*allocated_size_i[1]) ) begin
-
-        post_scramble_row_index  = 'b0;
-        post_scramble_tile_id    = 'b0;
-        // 1. `post_scramble_row_index` generation
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + shift_index[1])) & mask_row_index[1];
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + TileIdBits    )) & mask_row_index_n[1];
-
-        // 2. `post_scramble_tile_id` generation
-        post_scramble_tile_id   |= heap_tile_id & mask_tile_id[1];
-        post_scramble_tile_id   |= (address_i >> (ConstantBitsLSB + shift_index_sc[1])) & mask_tile_id_n[1];
-
-        address_o[HeapSeqTotalBits-1:ConstantBitsLSB] = {post_scramble_row_index, post_scramble_tile_id};
-        group_factor_o = group_factor_i[1];
-        allocated_size_o = allocated_size_i[1];
-      end else if ( (address_i >= start_addr_scheme_i[2]) && (address_i < start_addr_scheme_i[2]+MemSizePerRow*allocated_size_i[2]) ) begin
-
-        post_scramble_row_index  = 'b0;
-        post_scramble_tile_id    = 'b0;
-        // 1. `post_scramble_row_index` generation
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + shift_index[2])) & mask_row_index[2];
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + TileIdBits    )) & mask_row_index_n[2];
-
-        // 2. `post_scramble_tile_id` generation
-        post_scramble_tile_id   |= heap_tile_id & mask_tile_id[2];
-        post_scramble_tile_id   |= (address_i >> (ConstantBitsLSB + shift_index_sc[2])) & mask_tile_id_n[2];
-
-        address_o[HeapSeqTotalBits-1:ConstantBitsLSB] = {post_scramble_row_index, post_scramble_tile_id};
-        group_factor_o = group_factor_i[2];
-        allocated_size_o = allocated_size_i[2];
-      end else if ( (address_i >= start_addr_scheme_i[3]) && (address_i < start_addr_scheme_i[3]+MemSizePerRow*allocated_size_i[3]) ) begin
-
-        post_scramble_row_index  = 'b0;
-        post_scramble_tile_id    = 'b0;
-        // 1. `post_scramble_row_index` generation
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + shift_index[3])) & mask_row_index[3];
-        post_scramble_row_index |= (address_i >> (ConstantBitsLSB + TileIdBits    )) & mask_row_index_n[3];
-
-        // 2. `post_scramble_tile_id` generation
-        post_scramble_tile_id   |= heap_tile_id & mask_tile_id[3];
-        post_scramble_tile_id   |= (address_i >> (ConstantBitsLSB + shift_index_sc[3])) & mask_tile_id_n[3];
-
-        address_o[HeapSeqTotalBits-1:ConstantBitsLSB] = {post_scramble_row_index, post_scramble_tile_id};
-        group_factor_o = group_factor_i[3];
-        allocated_size_o = allocated_size_i[3];
+        group_factor_o   = NumTiles; // fully interleaved
+        allocated_size_o = num_bytes_i / MemSizePerRow;
+
+      // DAS address scrambling
+      end else begin
+
+        for (int p = 0; p < NumDASPartitions; p++) begin
+          if ( (address_i >= start_addr_scheme_i[p]) && (address_i < start_addr_scheme_i[p]+MemSizePerRow*allocated_size_i[p]) ) begin
+            address_o = '0;
+            address_o |= address_i & ((1 << (tile_index[p]+ConstantBitsLSB)) - 1);
+            address_o |= ((address_i >> (row_index[p]+tile_index[p]+ConstantBitsLSB)) << (tile_index[p]+ConstantBitsLSB)) & ((1 << (TileIdBits+ConstantBitsLSB)) - 1);
+            address_o |= ((address_i >> (tile_index[p]+ConstantBitsLSB)) << (TileIdBits + ConstantBitsLSB)) & ((1 << (row_index[p]+TileIdBits+ConstantBitsLSB)) - 1);
+            address_o |= address_i & ~((1 << (row_index[p]+TileIdBits+ConstantBitsLSB)) - 1);
+            group_factor_o   = group_factor_i[p];
+            allocated_size_o = allocated_size_i[p];
+          end
+        end
+
       end 
     end
 
@@ -177,6 +100,5 @@ module idma_address_scrambler #(
   // Check for unsupported configurations
   if (NumBanksPerTile < 2)
     $fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!");
-  if (HeapSeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0)
-    $fatal(1, "HeapSeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!");
+
 endmodule : idma_address_scrambler