Add ZCU104 board support

sw/boot/cheshire.zcu104.dts

@@ -0,0 +1,24 @@
+// Copyright 2025 lowRISC contributors.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Created by Abdelkadir Chantar <[email protected]> - Add device tree for ZCU104 board
+
+/include/ "cheshire.dtsi"
+
+/ {
+    model = "Digilent ZCU104 custom RV SoC";
+    compatible = "digilent,zcu104", "xlnx,zynqmp";
+
+    memory@80000000 {
+        device_type = "memory";
+        reg = <0x0 0x80000000 0x0 0x40000000>; // 1 GiB
+    };
+
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        // Add if you reserve space (e.g. framebuffer, firmware, etc.)
+    };
+};

sw/boot/cheshire.zcu104_vga.dts

@@ -0,0 +1,25 @@
+// Copyright 2025 lowRISC contributors.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Created by Abdelkadir Chantar <[email protected]> - Add vga support
+
+/include/ "cheshire.zcu104.dts"
+
+
+&chosen {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  ranges;
+  bootargs = "earlycon console=ttyS0,115200 root=/dev/ram rw";
+  stdout-path = "/soc/serial@3002000";  
+  framebuffer0: framebuffer@A0000000 {
+    compatible = "simple-framebuffer";
+    reg = <0x0 0xA0000000 0x0 (640 * 480 * 2)>;
+    width = <640>;
+    height = <480>;
+    stride = <(640 * 2)>;
+    format = "r5g6b5";
+    status = "okay";
+  };
+};

target/xilinx/constraints/zcu104.xdc

@@ -0,0 +1,201 @@
+# Copyright 2025 lowRISC contributors.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Created by Abdelkadir Chantar <[email protected]> - Add constraints for ZCU104 board
+
+#############
+# Sys Clock #
+#############
+
+# 125 MHz input clock
+set SYS_TCK 8
+create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p]
+
+# SoC clock is generated by clock wizard and its constraints
+# SoC clock outputs 50MHz
+set SOC_TCK 20.0
+set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk]
+
+#######
+# MIG #
+#######
+
+# Dram axi clock : 200 MHz (defined by MIG constraints)
+set MIG_TCK 5
+
+# False-path incoming reset
+set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn]
+set_false_path -hold -setup -through $MIG_RST_I
+
+# Constrain outgoing reset
+set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+set_false_path -hold -through $MIG_RST_O
+set_max_delay -through $MIG_RST_O $MIG_TCK
+
+# Limit delay across DRAM CDC (hold already false-pathed)
+# tclint-disable line-length
+set_max_delay -datapath_only \
+    -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
+    -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK
+set_max_delay -datapath_only \
+    -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
+    -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK
+# tclint-enable line-length
+
+###############
+# Assign Pins #
+###############
+
+# tclint-disable line-length, spacing
+
+set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS33 } [get_ports uart_rx_i ];# "USB UART Rx" PMOD - PIN1
+set_property -dict { PACKAGE_PIN H8 IOSTANDARD LVCMOS33 } [get_ports uart_tx_o ];# "USB UART Tx" PMOD - PIN3
+
+# Jtag GPIOs goes to the FMC XM105 where the debug cable is connected (example Digilent HS2)
+set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i   ];# "PMOD - PIN2" -  BD0
+set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i   ];# "PMOD - PIN4" -  BD1
+set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o   ];# "PMOD - PIN5" -  BD2
+set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i   ];# "PMOD - PIN7" -  BD3
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni ];
+
+
+# Clock diff @ 125MHz
+set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVDS} [get_ports sys_clk_p];# "CLK_125MHZ_P"
+set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVDS} [get_ports sys_clk_n];# "CLK_125MHZ_N"
+
+# boot mode
+set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS12} [get_ports boot_mode_i[0]];
+set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS12} [get_ports boot_mode_i[1]];
+
+
+# Active high reset
+set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports sys_resetn];
+
+
+########
+# DRAM #
+########
+
+set_property PACKAGE_PIN AH18       [get_ports c0_sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p]
+set_property PACKAGE_PIN AH17       [get_ports "c0_sys_clk_n"]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n]
+
+set_property PACKAGE_PIN AG20 [get_ports {c0_ddr4_dq[4]}]
+set_property PACKAGE_PIN AF23 [get_ports {c0_ddr4_dqs_t[0]}]
+set_property PACKAGE_PIN AG23 [get_ports {c0_ddr4_dqs_c[0]}]
+set_property PACKAGE_PIN AE14 [get_ports {c0_ddr4_dq[38]}]
+set_property PACKAGE_PIN AD14 [get_ports {c0_ddr4_dq[39]}]
+set_property PACKAGE_PIN AG19 [get_ports {c0_ddr4_dq[5]}]
+set_property PACKAGE_PIN AC12 [get_ports {c0_ddr4_dqs_t[4]}]
+set_property PACKAGE_PIN AD12 [get_ports {c0_ddr4_dqs_c[4]}]
+set_property PACKAGE_PIN AF13 [get_ports {c0_ddr4_dq[36]}]
+set_property PACKAGE_PIN AH22 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+set_property PACKAGE_PIN AG21 [get_ports {c0_ddr4_dq[7]}]
+set_property PACKAGE_PIN AH21 [get_ports {c0_ddr4_dq[6]}]
+set_property PACKAGE_PIN AE13 [get_ports {c0_ddr4_dq[37]}]
+set_property PACKAGE_PIN AB14 [get_ports c0_ddr4_reset_n]
+set_property PACKAGE_PIN AF11 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+set_property PACKAGE_PIN AN19 [get_ports {c0_ddr4_dq[30]}]
+set_property PACKAGE_PIN AM19 [get_ports {c0_ddr4_dq[31]}]
+set_property PACKAGE_PIN AE15 [get_ports {c0_ddr4_odt[0]}]
+set_property PACKAGE_PIN AP22 [get_ports {c0_ddr4_dq[28]}]
+set_property PACKAGE_PIN AP21 [get_ports {c0_ddr4_dq[29]}]
+set_property PACKAGE_PIN AP9  [get_ports {c0_ddr4_dq[62]}]
+set_property PACKAGE_PIN AN11 [get_ports {c0_ddr4_dq[61]}]
+set_property PACKAGE_PIN AP11 [get_ports {c0_ddr4_dq[60]}]
+set_property PACKAGE_PIN AC17 [get_ports c0_ddr4_act_n]
+set_property PACKAGE_PIN AM21 [get_ports {c0_ddr4_dqs_t[3]}]
+set_property PACKAGE_PIN AN21 [get_ports {c0_ddr4_dqs_c[3]}]
+set_property PACKAGE_PIN AP10 [get_ports {c0_ddr4_dq[63]}]
+set_property PACKAGE_PIN AN12 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+set_property PACKAGE_PIN AD17 [get_ports {c0_ddr4_cke[0]}]
+set_property PACKAGE_PIN AA15 [get_ports {c0_ddr4_cs_n[0]}]
+set_property PACKAGE_PIN AP19 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+set_property PACKAGE_PIN AN8  [get_ports {c0_ddr4_dqs_c[7]}]
+set_property PACKAGE_PIN AN9  [get_ports {c0_ddr4_dqs_t[7]}]
+set_property PACKAGE_PIN AL12 [get_ports {c0_ddr4_dq[52]}]
+set_property PACKAGE_PIN AC16 [get_ports {c0_ddr4_bg[0]}]
+set_property PACKAGE_PIN AL16 [get_ports {c0_ddr4_ba[1]}]
+set_property PACKAGE_PIN AK19 [get_ports {c0_ddr4_dq[20]}]
+set_property PACKAGE_PIN AL23 [get_ports {c0_ddr4_dq[22]}]
+set_property PACKAGE_PIN AL22 [get_ports {c0_ddr4_dq[23]}]
+set_property PACKAGE_PIN AL10 [get_ports {c0_ddr4_dq[54]}]
+set_property PACKAGE_PIN AK12 [get_ports {c0_ddr4_dq[53]}]
+set_property PACKAGE_PIN AK13 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+set_property PACKAGE_PIN AA16 [get_ports {c0_ddr4_adr[14]}]
+set_property PACKAGE_PIN AJ19 [get_ports {c0_ddr4_dq[21]}]
+set_property PACKAGE_PIN AK22 [get_ports {c0_ddr4_dqs_t[2]}]
+set_property PACKAGE_PIN AK23 [get_ports {c0_ddr4_dqs_c[2]}]
+set_property PACKAGE_PIN AL11 [get_ports {c0_ddr4_dq[55]}]
+set_property PACKAGE_PIN AK18 [get_ports {c0_ddr4_adr[13]}]
+set_property PACKAGE_PIN AL18 [get_ports {c0_ddr4_adr[12]}]
+set_property PACKAGE_PIN AB16 [get_ports {c0_ddr4_bg[1]}]
+set_property PACKAGE_PIN AA14 [get_ports {c0_ddr4_adr[15]}]
+set_property PACKAGE_PIN AL20 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+set_property PACKAGE_PIN AK8  [get_ports {c0_ddr4_dqs_t[6]}]
+set_property PACKAGE_PIN AL8  [get_ports {c0_ddr4_dqs_c[6]}]
+set_property PACKAGE_PIN AG13 [get_ports {c0_ddr4_dq[45]}]
+set_property PACKAGE_PIN AH13 [get_ports {c0_ddr4_dq[44]}]
+set_property PACKAGE_PIN AK15 [get_ports {c0_ddr4_adr[11]}]
+set_property PACKAGE_PIN AK14 [get_ports {c0_ddr4_adr[10]}]
+set_property PACKAGE_PIN AF16 [get_ports {c0_ddr4_adr[4]}]
+set_property PACKAGE_PIN AC19 [get_ports {c0_ddr4_dq[14]}]
+set_property PACKAGE_PIN AH11 [get_ports {c0_ddr4_dq[47]}]
+set_property PACKAGE_PIN AJ11 [get_ports {c0_ddr4_dq[46]}]
+set_property PACKAGE_PIN AH12 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+set_property PACKAGE_PIN AJ17 [get_ports {c0_ddr4_adr[9]}]
+set_property PACKAGE_PIN AA18 [get_ports {c0_ddr4_dqs_t[1]}]
+set_property PACKAGE_PIN AB18 [get_ports {c0_ddr4_dqs_c[1]}]
+set_property PACKAGE_PIN AE20 [get_ports {c0_ddr4_dq[12]}]
+set_property PACKAGE_PIN AB19 [get_ports {c0_ddr4_dq[15]}]
+set_property PACKAGE_PIN AH9  [get_ports {c0_ddr4_dqs_c[5]}]
+set_property PACKAGE_PIN AG9  [get_ports {c0_ddr4_dqs_t[5]}]
+set_property PACKAGE_PIN AF15 [get_ports {c0_ddr4_adr[3]}]
+set_property PACKAGE_PIN AF17 [get_ports {c0_ddr4_adr[7]}]
+set_property PACKAGE_PIN AH14 [get_ports {c0_ddr4_adr[6]}]
+set_property PACKAGE_PIN AG14 [get_ports {c0_ddr4_adr[1]}]
+set_property PACKAGE_PIN AE18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+set_property PACKAGE_PIN AD20 [get_ports {c0_ddr4_dq[13]}]
+set_property PACKAGE_PIN AH16 [get_ports {c0_ddr4_adr[0]}]
+set_property PACKAGE_PIN AG15 [get_ports {c0_ddr4_adr[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {c0_ddr4_adr[8]}]
+set_property PACKAGE_PIN AD15 [get_ports {c0_ddr4_adr[16]}]
+
+set_property PACKAGE_PIN AJ14 [get_ports {c0_ddr4_adr[5]}]
+set_property PACKAGE_PIN AL15 [get_ports {c0_ddr4_ba[0]}]
+set_property PACKAGE_PIN AF18 [get_ports {c0_ddr4_ck_t[0]}]
+set_property PACKAGE_PIN AM11 [get_ports {c0_ddr4_dq[59]}]
+set_property PACKAGE_PIN AM10 [get_ports {c0_ddr4_dq[58]}]
+set_property PACKAGE_PIN AM9  [get_ports {c0_ddr4_dq[57]}]
+set_property PACKAGE_PIN AM8  [get_ports {c0_ddr4_dq[56]}]
+set_property PACKAGE_PIN AJ10 [get_ports {c0_ddr4_dq[51]}]
+set_property PACKAGE_PIN AK10 [get_ports {c0_ddr4_dq[50]}]
+set_property PACKAGE_PIN AJ9  [get_ports {c0_ddr4_dq[49]}]
+set_property PACKAGE_PIN AK9  [get_ports {c0_ddr4_dq[48]}]
+set_property PACKAGE_PIN AG11 [get_ports {c0_ddr4_dq[43]}]
+set_property PACKAGE_PIN AG10 [get_ports {c0_ddr4_dq[42]}]
+set_property PACKAGE_PIN AF8  [get_ports {c0_ddr4_dq[41]}]
+set_property PACKAGE_PIN AG8  [get_ports {c0_ddr4_dq[40]}]
+set_property PACKAGE_PIN AE12 [get_ports {c0_ddr4_dq[35]}]
+set_property PACKAGE_PIN AF12 [get_ports {c0_ddr4_dq[34]}]
+set_property PACKAGE_PIN AB13 [get_ports {c0_ddr4_dq[33]}]
+set_property PACKAGE_PIN AC13 [get_ports {c0_ddr4_dq[32]}]
+set_property PACKAGE_PIN AN22 [get_ports {c0_ddr4_dq[27]}]
+set_property PACKAGE_PIN AP23 [get_ports {c0_ddr4_dq[26]}]
+set_property PACKAGE_PIN AM23 [get_ports {c0_ddr4_dq[25]}]
+set_property PACKAGE_PIN AN23 [get_ports {c0_ddr4_dq[24]}]
+set_property PACKAGE_PIN AJ20 [get_ports {c0_ddr4_dq[19]}]
+set_property PACKAGE_PIN AK20 [get_ports {c0_ddr4_dq[18]}]
+set_property PACKAGE_PIN AJ21 [get_ports {c0_ddr4_dq[17]}]
+set_property PACKAGE_PIN AJ22 [get_ports {c0_ddr4_dq[16]}]
+set_property PACKAGE_PIN AC18 [get_ports {c0_ddr4_dq[11]}]
+set_property PACKAGE_PIN AD19 [get_ports {c0_ddr4_dq[10]}]
+set_property PACKAGE_PIN AA19 [get_ports {c0_ddr4_dq[9]}]
+set_property PACKAGE_PIN AA20 [get_ports {c0_ddr4_dq[8]}]
+set_property PACKAGE_PIN AF21 [get_ports {c0_ddr4_dq[3]}]
+set_property PACKAGE_PIN AF22 [get_ports {c0_ddr4_dq[2]}]
+set_property PACKAGE_PIN AE23 [get_ports {c0_ddr4_dq[1]}]
+set_property PACKAGE_PIN AE24 [get_ports {c0_ddr4_dq[0]}]

target/xilinx/scripts/common.tcl

@@ -16,6 +16,12 @@ set fpart(vcu128) "xcvu37p-fsvh2892-2L-e"
 set hwdev(vcu128) "xcvu37p_0"
 set cfgmp(vcu128) "mt25qu02g-spi-x1_x2_x4"
 
+# zcu104 board params
+set bpart(zcu104) "xilinx.com:zcu104:part0:1.1"
+set fpart(zcu104) "xczu7ev-ffvc1156-2-e"
+set hwdev(zcu104) "xcvu9p_0"
+#set cfgmp(zcu104) "mt25qu02g-spi-x1_x2_x4"
+
 
 # Initialize an implementation project
 proc init_impl {xilinx_root argc argv} {

target/xilinx/scripts/impl_ip.tcl

@@ -5,6 +5,7 @@
 # Florian Zaruba <[email protected]>
 # Cyril Koenig <[email protected]>
 # Paul Scheffler <[email protected]>
+# Abdelkadir Chantar <[email protected]>
 
 # Initialize implementation
 set xilinx_root [file dirname [file dirname [file normalize [info script]]]]
@@ -87,6 +88,43 @@ switch $proj {
                     CONFIG.CLKOUT4_PHASE_ERROR {89.971} \
                     ] [get_ips $proj]
             }
+            zcu104 {
+                set_property -dict [list \
+                    CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
+                    CONFIG.RESET_BOARD_INTERFACE {Custom} \
+                    CONFIG.USE_RESET {true} \
+                    CONFIG.PRIM_SOURCE {No_buffer} \
+                    CONFIG.PRIM_IN_FREQ {125.000} \
+                    CONFIG.CLKOUT1_USED {true} \
+                    CONFIG.CLKOUT2_USED {true} \
+                    CONFIG.CLKOUT3_USED {true} \
+                    CONFIG.CLKOUT4_USED {true} \
+                    CONFIG.CLK_OUT1_PORT {clk_50} \
+                    CONFIG.CLK_OUT2_PORT {clk_48} \
+                    CONFIG.CLK_OUT3_PORT {clk_20} \
+                    CONFIG.CLK_OUT4_PORT {clk_10} \
+                    CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
+                    CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {48.000} \
+                    CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \
+                    CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
+                    CONFIG.CLKIN1_JITTER_PS {50.0} \
+                    CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \
+                    CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
+                    CONFIG.MMCM_CLKOUT1_DIVIDE {24} \
+                    CONFIG.MMCM_CLKOUT2_DIVIDE {25} \
+                    CONFIG.MMCM_CLKOUT3_DIVIDE {60} \
+                    CONFIG.MMCM_CLKOUT4_DIVIDE {120} \
+                    CONFIG.NUM_OUT_CLKS {4} \
+                    CONFIG.CLKOUT1_JITTER {196.543} \
+                    CONFIG.CLKOUT1_PHASE_ERROR {222.305} \
+                    CONFIG.CLKOUT2_JITTER {197.699} \
+                    CONFIG.CLKOUT2_PHASE_ERROR {222.305} \
+                    CONFIG.CLKOUT3_JITTER {227.146} \
+                    CONFIG.CLKOUT3_PHASE_ERROR {222.305} \
+                    CONFIG.CLKOUT4_JITTER {261.444} \
+                    CONFIG.CLKOUT4_PHASE_ERROR {222.305} \
+                    ] [get_ips $proj]
+            }
             default { nocfgexit $proj $board }
         }
     }
@@ -116,6 +154,17 @@ switch $proj {
                     CONFIG.C_NUM_PROBE_IN {0} \
                     ] [get_ips $proj]
             }
+            zcu104 {
+                set_property -dict [list \
+                    CONFIG.C_NUM_PROBE_OUT {3} \
+                    CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \
+                    CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \
+                    CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \
+                    CONFIG.C_PROBE_OUT1_WIDTH {2} \
+                    CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
+                    CONFIG.C_NUM_PROBE_IN {0} \
+                    ] [get_ips $proj]
+            }
             default { nocfgexit $proj $board }
         }
     }
@@ -162,6 +211,29 @@ switch $proj {
                     CONFIG.C0.DDR4_AxiSelection {true} \
                     ] [get_ips $proj]
             }
+            zcu104 {
+                set_property -dict [list \
+                    CONFIG.C0.DDR4_Clamshell {false} \
+                    CONFIG.System_Clock {Differential} \
+                    CONFIG.Reference_Clock {Differential} \
+                    CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \
+                    CONFIG.C0.DDR4_InputClockPeriod {3333} \
+                    CONFIG.C0.DDR4_TimePeriod {1250} \
+                    CONFIG.C0.DDR4_CLKOUT0_DIVIDE {7} \
+                    CONFIG.C0.DDR4_DataWidth {64} \
+                    CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
+                    CONFIG.C0.DDR4_Ecc {false} \
+                    CONFIG.C0.DDR4_AxiSelection {true} \
+                    CONFIG.C0.DDR4_AxiDataWidth {512} \
+                    CONFIG.C0.DDR4_AxiAddressWidth {32} \
+                    CONFIG.C0.DDR4_AxiIDWidth {8} \
+                    CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
+                    CONFIG.C0.BANK_GROUP_WIDTH {2} \
+                    CONFIG.C0.DDR4_isCustom {false} \
+                    CONFIG.C0.CS_WIDTH {1} \
+                    ] [get_ips $proj]
+            }
+
             default { nocfgexit $proj $board }
         }
     }

target/xilinx/src/cheshire_top_xilinx.sv

@@ -74,6 +74,15 @@ module cheshire_top_xilinx import cheshire_pkg::*; (
   output logic [4:0]  vga_blue_o,
 `endif
 
+`ifdef USE_DDR4
+  `ifdef TARGET_ZCU104
+    `TARGET_ZCU104_INTF
+  `endif
+`endif
+`ifdef USE_DDR3
+  `DDR3_INTF
+`endif
+
 `ifdef USE_QSPI
 `ifndef USE_STARTUPE3
 `ifndef USE_STARTUPE2
@@ -85,13 +94,6 @@ module cheshire_top_xilinx import cheshire_pkg::*; (
 `endif
 `endif
 
-`ifdef USE_DDR4
-  `DDR4_INTF
-`endif
-`ifdef USE_DDR3
-  `DDR3_INTF
-`endif
-
   output logic  uart_tx_o,
   input  logic  uart_rx_i,