Testing hyperram on FPGA

[CyrilKoe]

[WIP] this PR aims to test hyper-ram usability on FPGA (both vanilla and BD flow) for basic R/W/X bare metal

• Added HYPERRAM flow in CI
• Enhanced automatic CDC script in carfield_islands.tcl
• Added hyperbus pins assignment constraints
• Cleaned all unused pins assignements (large diff)
• Added pin assignments for JTAG and hyperram in dedicated files
• Removed irrelevant zcu102.xdc file
• Modified carfield_xilinx_ip.v to fit to the Verilog standard (large diff)

It is designed for the black FMC hyperram/hyperflash board (Ver:A 02.2021) available at IIS.

• Test bare-metal VCU128 bd

make car-xil-all GEN_NO_HYPERBUS=0 CARFIELD_CONFIG=carfield_l2dual_periph GEN_EXT_JTAG=0 XILINX_FLAVOR=bd VIVADO_MODE=gui XILINX_BOARD=vcu128 

• Test bare-metal VCU128 vanilla

make car-xil-all GEN_NO_HYPERBUS=0 CARFIELD_CONFIG=carfield_l2dual_safe_periph GEN_EXT_JTAG=0 XILINX_FLAVOR=vanilla VIVADO_MODE=batch XILINX_BOARD=vcu128

Note: Using the FMC requires removing the debug FMC thus setting GEN_EXT_JTAG=0

[alex96295]

@CyrilKoe , can you brief me on the status of this PR? Is it supposed to be cleaned up and merged, or can be closed?

[CyrilKoe]

@CyrilKoe , can you brief me on the status of this PR? Is it supposed to be cleaned up and merged, or can be closed?

@alex96295 Currently, it is stalled; some parts of it would benefit from being added, but a bit of testing is still needed. Do we still have the hyperram module available?

[alex96295]

@CyrilKoe , can you brief me on the status of this PR? Is it supposed to be cleaned up and merged, or can be closed?

@alex96295 Currently, it is stalled; some parts of it would benefit from being added, but a bit of testing is still needed. Do we still have the hyperram module available?

yes, it's in my office