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@jmdeharor
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Some files already have the XSIM ifndef to remove the default disable blocks (https://github.com/pulp-platform/axi/blob/master/src/axi_xbar_unmuxed.sv), which are not supported by XSIM. This MR completes this task to make all files consistent, and ensuring they can be simulated with Vivado.

@cousteaulecommandant
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I got this issue too. It results in the error message The SystemVerilog feature "Default Disable iff declaration" is not supported yet for simulation. when trying to simulate in Vivado. Apparently, XSIM doesn't support default disable iff constructs. (As the original poster mentioned, these constructs are already disabled in some files for XSIM as well as Verilator, but only for Verilator on other files. This PR would fix that.)

For now, the workaround I had to use was to add VERILATOR to the list of macro definitions in the simulation settings of Vivado in my local project.

PS: This comment suggests that newer versions of Vivado need to use the macro XILINX_SIMULATOR rather than XSIM. Maybe all three should be checked?

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