Bump Cheshire to include Culsans and TLB ECC protection #40
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… in bender-common.
…ference (pulp-platform#262) * WIP: add wce test. * Fix `buffer` accesses in `pulp-offload-intf.c` * Let `pulp_boot_default` be defined by `elf2header.py` * Point to yt/carfield branch for the `regression_tests` * Fix `carfield.mk` indentation * Correctly filter out `CAR_ELFLOAD_PULPD_INTF_SRC_C` from `CAR_SW_TEST_SRCS_C`
* Bump dependencies and align testbench with new Cheshire JTAG tasks. * Fix connections. * Align cache-enable CSR with OpenHW recent changes... * Add draft CI flow. * Use normal printf in `Helloworld`. * Update nonfree rules. * Fix parameter declaration in L2 Ecc asyncronoys buses. * Fix PULP cluster EOC and busy enable connections. * Update nonfree. * Bump nonfree. * Bump nonfree to copy uImage in dedicated `astral` folder. * Apply suggestions from code review Co-authored-by: Michael Rogenmoser <[email protected]> --------- Co-authored-by: Yvan Tortorella <[email protected]> Co-authored-by: Michael Rogenmoser <[email protected]>
Left commented old INTEL16 implementation of the PLL, as a reference.
Update README.md Update README.md Fixing simulation flow: WIP Update README.md
…dded behavioural padframe dependency to Bender Update README.md Debugging (WIP)
…Pad behavioural model; Added necessary package; Removed memory initialization in the TB Fixes after last rebase Fixes after the last rebase Fixes after the last rebase Fixes after rebase
…f spatz and safety island
… Updated the TB accordingly. IMPORTANT: the FLL is slow (13.61MHz instead of the nominal 42MHz) and this causes issues with tests (e.g. the VIP of the hyperram complains that the CS is too slow)
Co-authored-by: Victor Isachi <[email protected]>
…ixed FLL propagation to SECD/RT clocks (#44) Co-authored-by: Victor Isachi <[email protected]>
Co-authored-by: Victor Isachi <[email protected]>
* Fix Clock Domains numbers * Fix default value of security domain clock mux selector
…ed readability of memory map (#48) Co-authored-by: Victor Isachi <[email protected]>
* Removing function waitgin for pad config to allow secd stand alone tests' execution * Fixing tests, using 50MHz of JTAG instead of 55,something MHz. * Bumping OpenTitan, updated bootrom with padframe config for SPI host. * Hardcode OpenTitan ans Safety Island JTAG clock frequencies to 50 MHz. * Fix typo in secure domain generation. --------- Co-authored-by: Maicol Ciani <[email protected]> Co-authored-by: Yvan Tortorella <[email protected]>
yvantor
approved these changes
Sep 4, 2024
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