Added FLL and Padframe drivers; Updated FLL test to use the driver; F…

…ixed FLL propagation to SECD/RT clocks (#44)

Co-authored-by: Victor Isachi <[email protected]>

hw/astral_wrap.sv

@@ -400,7 +400,7 @@ module astral_wrap
     .DIV_VALUE            ( 100  ),
     .ENABLE_CLOCK_IN_RESET( 1'b1 )
   ) i_rt_clk_div (
-    .clk_i          ( clk_fll_out[3] ),
+    .clk_i          ( clk_fll_out[4] ),
     .rst_ni         ( pwr_on_rst_n   ),
     .en_i           ( 1'b1           ),
     .test_mode_en_i ( 1'b0           ),

sw/include/car_memory_map.h

@@ -188,10 +188,186 @@ extern void *__base_l2;
 #define TCTM_STREAMER_APB_TC_BUFFER_BASE  CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TC_BUFFER_OFFS
 #define TCTM_STREAMER_APB_TX_BUFFER_BASE  CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TX_BUFFER_OFFS
 
-// PLL
-#define CAR_PLL_BASE_ADDRESS         0x21003000
-#define PLL_ADDR_SPACE               0x200
-#define PLL_BASE_ADDRESS(id)         (CAR_PLL_BASE_ADDRESS + (id+1)*PLL_ADDR_SPACE)
+// FLL
+#define FLL_BASE_ADDRESS     0x21003000
+#define FLL_ADDR_SPACE       0x20
+#define FLL_HOST_ID          0x0
+#define FLL_PERIPH_ID        0x1
+#define FLL_ALT_ID           0x2
+#define FLL_SECD_ID          0x3
+#define FLL_RT_ID            0x4
+#define FLL_BASE_ADDRESS(id) (FLL_BASE_ADDRESS + (id)*FLL_ADDR_SPACE)
+
+#define FLL_STATUS_REG_I     0x00    
+#define FLL_CONFIG_REG_I     0x08    
+#define FLL_CONFIG_REG_II    0x10    
+#define FLL_INTEGR_REG       0x18    
+
+// Padframe
+#define PADFRAME_BASE_ADDRESS                         0x21000000
+
+#define PADFRAME_CONFIG_INFO                          0x0
+#define PADFRAME_CONFIG_MUXED_V_00_CFG                0x4
+#define PADFRAME_CONFIG_MUXED_V_00_MUX_SEL            0x8
+#define PADFRAME_CONFIG_MUXED_V_01_CFG                0xc
+#define PADFRAME_CONFIG_MUXED_V_01_MUX_SEL            0x10
+#define PADFRAME_CONFIG_MUXED_V_02_CFG                0x14
+#define PADFRAME_CONFIG_MUXED_V_02_MUX_SEL            0x18
+#define PADFRAME_CONFIG_MUXED_V_03_CFG                0x1c
+#define PADFRAME_CONFIG_MUXED_V_03_MUX_SEL            0x20
+#define PADFRAME_CONFIG_MUXED_V_04_CFG                0x24
+#define PADFRAME_CONFIG_MUXED_V_04_MUX_SEL            0x28
+#define PADFRAME_CONFIG_MUXED_V_05_CFG                0x2c
+#define PADFRAME_CONFIG_MUXED_V_05_MUX_SEL            0x30
+#define PADFRAME_CONFIG_MUXED_V_06_CFG                0x34
+#define PADFRAME_CONFIG_MUXED_V_06_MUX_SEL            0x38
+#define PADFRAME_CONFIG_MUXED_V_07_CFG                0x3c
+#define PADFRAME_CONFIG_MUXED_V_07_MUX_SEL            0x40
+#define PADFRAME_CONFIG_MUXED_V_08_CFG                0x44
+#define PADFRAME_CONFIG_MUXED_V_08_MUX_SEL            0x48
+#define PADFRAME_CONFIG_MUXED_V_09_CFG                0x4c
+#define PADFRAME_CONFIG_MUXED_V_09_MUX_SEL            0x50
+#define PADFRAME_CONFIG_MUXED_V_10_CFG                0x54
+#define PADFRAME_CONFIG_MUXED_V_10_MUX_SEL            0x58
+#define PADFRAME_CONFIG_MUXED_V_11_CFG                0x5c
+#define PADFRAME_CONFIG_MUXED_V_11_MUX_SEL            0x60
+#define PADFRAME_CONFIG_MUXED_V_12_CFG                0x64
+#define PADFRAME_CONFIG_MUXED_V_12_MUX_SEL            0x68
+#define PADFRAME_CONFIG_MUXED_V_13_CFG                0x6c
+#define PADFRAME_CONFIG_MUXED_V_13_MUX_SEL            0x70
+#define PADFRAME_CONFIG_MUXED_V_14_CFG                0x74
+#define PADFRAME_CONFIG_MUXED_V_14_MUX_SEL            0x78
+#define PADFRAME_CONFIG_MUXED_V_15_CFG                0x7c
+#define PADFRAME_CONFIG_MUXED_V_15_MUX_SEL            0x80
+#define PADFRAME_CONFIG_MUXED_V_16_CFG                0x84
+#define PADFRAME_CONFIG_MUXED_V_16_MUX_SEL            0x88
+#define PADFRAME_CONFIG_MUXED_V_17_CFG                0x8c
+#define PADFRAME_CONFIG_MUXED_V_17_MUX_SEL            0x90
+#define PADFRAME_CONFIG_MUXED_H_00_CFG                0x94
+#define PADFRAME_CONFIG_MUXED_H_00_MUX_SEL            0x98
+#define PADFRAME_CONFIG_MUXED_H_01_CFG                0x9c
+#define PADFRAME_CONFIG_MUXED_H_01_MUX_SEL            0xa0
+#define PADFRAME_CONFIG_MUXED_H_02_CFG                0xa4
+#define PADFRAME_CONFIG_MUXED_H_02_MUX_SEL            0xa8
+#define PADFRAME_CONFIG_MUXED_H_03_CFG                0xac
+#define PADFRAME_CONFIG_MUXED_H_03_MUX_SEL            0xb0
+
+#define PADFRAME_MUXED_H_00_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3        0x1
+#define PADFRAME_MUXED_H_00_SEL_GPIO_IO_H_0           0x2
+#define PADFRAME_MUXED_H_00_SEL_HPC_SAMPLE            0x3
+#define PADFRAME_MUXED_H_00_SEL_SERIAL_LINK_O_H_0     0x4
+#define PADFRAME_MUXED_H_01_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_H_01_SEL_ETHERNET_MD           0x1
+#define PADFRAME_MUXED_H_01_SEL_GPIO_IO_H_1           0x2
+#define PADFRAME_MUXED_H_01_SEL_LLC_LINE_0            0x3
+#define PADFRAME_MUXED_H_01_SEL_SERIAL_LINK_O_H_1     0x4
+#define PADFRAME_MUXED_H_02_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC          0x1
+#define PADFRAME_MUXED_H_02_SEL_GPIO_IO_H_2           0x2
+#define PADFRAME_MUXED_H_02_SEL_LLC_LINE_1            0x3
+#define PADFRAME_MUXED_H_02_SEL_SERIAL_LINK_O_H_2     0x4
+#define PADFRAME_MUXED_H_03_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N        0x1
+#define PADFRAME_MUXED_H_03_SEL_GPIO_IO_H_3           0x2
+#define PADFRAME_MUXED_H_03_SEL_OBT_EXT_CLK           0x3
+#define PADFRAME_MUXED_H_03_SEL_SERIAL_LINK_O_H_3     0x4
+#define PADFRAME_MUXED_V_00_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_00_SEL_CAN_RX                0x1
+#define PADFRAME_MUXED_V_00_SEL_GPIO_IO_V_0           0x2
+#define PADFRAME_MUXED_V_00_SEL_I2C_SDA               0x3
+#define PADFRAME_MUXED_V_00_SEL_SPI_SCK               0x4
+#define PADFRAME_MUXED_V_00_SEL_SPI_OT_SCK            0x5
+#define PADFRAME_MUXED_V_01_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_01_SEL_CAN_TX                0x1
+#define PADFRAME_MUXED_V_01_SEL_GPIO_IO_V_1           0x2
+#define PADFRAME_MUXED_V_01_SEL_I2C_SCL               0x3
+#define PADFRAME_MUXED_V_01_SEL_SPI_CSB_0             0x4
+#define PADFRAME_MUXED_V_01_SEL_SPI_OT_CSB            0x5
+#define PADFRAME_MUXED_V_02_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_02_SEL_GPIO_IO_V_2           0x1
+#define PADFRAME_MUXED_V_02_SEL_SPI_CSB_1             0x2
+#define PADFRAME_MUXED_V_02_SEL_SPI_OT_SD_0           0x3
+#define PADFRAME_MUXED_V_03_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_03_SEL_GPIO_IO_V_3           0x1
+#define PADFRAME_MUXED_V_03_SEL_SPI_SD_0              0x2
+#define PADFRAME_MUXED_V_03_SEL_SPI_OT_SD_1           0x3
+#define PADFRAME_MUXED_V_04_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_04_SEL_GPIO_IO_V_4           0x1
+#define PADFRAME_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I 0x2
+#define PADFRAME_MUXED_V_04_SEL_SPI_SD_1              0x3
+#define PADFRAME_MUXED_V_04_SEL_SPI_OT_SD_2           0x4
+#define PADFRAME_MUXED_V_05_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_05_SEL_GPIO_IO_V_5           0x1
+#define PADFRAME_MUXED_V_05_SEL_SERIAL_LINK_I_0       0x2
+#define PADFRAME_MUXED_V_05_SEL_SPI_SD_2              0x3
+#define PADFRAME_MUXED_V_05_SEL_SPI_OT_SD_3           0x4
+#define PADFRAME_MUXED_V_06_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_06_SEL_GPIO_IO_V_6           0x1
+#define PADFRAME_MUXED_V_06_SEL_SERIAL_LINK_I_1       0x2
+#define PADFRAME_MUXED_V_06_SEL_SPI_SD_3              0x3
+#define PADFRAME_MUXED_V_07_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK         0x1
+#define PADFRAME_MUXED_V_07_SEL_GPIO_IO_V_7           0x2
+#define PADFRAME_MUXED_V_07_SEL_PLL_IO_0              0x3
+#define PADFRAME_MUXED_V_07_SEL_SERIAL_LINK_I_2       0x4
+#define PADFRAME_MUXED_V_07_SEL_TC_ACTIVE             0x5
+#define PADFRAME_MUXED_V_08_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL        0x1
+#define PADFRAME_MUXED_V_08_SEL_GPIO_IO_V_8           0x2
+#define PADFRAME_MUXED_V_08_SEL_PLL_IO_1              0x3
+#define PADFRAME_MUXED_V_08_SEL_SERIAL_LINK_I_3       0x4
+#define PADFRAME_MUXED_V_08_SEL_TC_CLK                0x5
+#define PADFRAME_MUXED_V_09_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0        0x1
+#define PADFRAME_MUXED_V_09_SEL_GPIO_IO_V_9           0x2
+#define PADFRAME_MUXED_V_09_SEL_PLL_IO_2              0x3
+#define PADFRAME_MUXED_V_09_SEL_SERIAL_LINK_I_4       0x4
+#define PADFRAME_MUXED_V_09_SEL_TC_DATA               0x5
+#define PADFRAME_MUXED_V_10_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1        0x1
+#define PADFRAME_MUXED_V_10_SEL_GPIO_IO_V_10          0x2
+#define PADFRAME_MUXED_V_10_SEL_PLL_IO_3              0x3
+#define PADFRAME_MUXED_V_10_SEL_PTME_CLK              0x4
+#define PADFRAME_MUXED_V_10_SEL_SERIAL_LINK_I_5       0x5
+#define PADFRAME_MUXED_V_11_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2        0x1
+#define PADFRAME_MUXED_V_11_SEL_GPIO_IO_V_11          0x2
+#define PADFRAME_MUXED_V_11_SEL_PLL_IO_4              0x3
+#define PADFRAME_MUXED_V_11_SEL_PTME_ENC              0x4
+#define PADFRAME_MUXED_V_11_SEL_SERIAL_LINK_I_6       0x5
+#define PADFRAME_MUXED_V_12_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3        0x1
+#define PADFRAME_MUXED_V_12_SEL_GPIO_IO_V_12          0x2
+#define PADFRAME_MUXED_V_12_SEL_PLL_IO_5              0x3
+#define PADFRAME_MUXED_V_12_SEL_PTME_SYNC             0x4
+#define PADFRAME_MUXED_V_12_SEL_SERIAL_LINK_I_7       0x5
+#define PADFRAME_MUXED_V_13_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK         0x1
+#define PADFRAME_MUXED_V_13_SEL_GPIO_IO_V_13          0x2
+#define PADFRAME_MUXED_V_13_SEL_PLL_IO_6              0x3
+#define PADFRAME_MUXED_V_13_SEL_PTME_EXT_CLK          0x4
+#define PADFRAME_MUXED_V_13_SEL_SERIAL_LINK_RCV_CLK_O 0x5
+#define PADFRAME_MUXED_V_14_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL        0x1
+#define PADFRAME_MUXED_V_14_SEL_GPIO_IO_V_14          0x2
+#define PADFRAME_MUXED_V_14_SEL_HPC_ADDR_0            0x3
+#define PADFRAME_MUXED_V_14_SEL_SERIAL_LINK_O_V_0     0x4
+#define PADFRAME_MUXED_V_15_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0        0x1
+#define PADFRAME_MUXED_V_15_SEL_GPIO_IO_V_15          0x2
+#define PADFRAME_MUXED_V_15_SEL_HPC_ADDR_1            0x3
+#define PADFRAME_MUXED_V_15_SEL_SERIAL_LINK_O_V_1     0x4
+#define PADFRAME_MUXED_V_16_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1        0x1
+#define PADFRAME_MUXED_V_16_SEL_GPIO_IO_V_16          0x2
+#define PADFRAME_MUXED_V_16_SEL_HPC_ADDR_2            0x3
+#define PADFRAME_MUXED_V_16_SEL_SERIAL_LINK_O_V_2     0x4
+#define PADFRAME_MUXED_V_17_SEL_DEFAULT               0x0
+#define PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2        0x1
+#define PADFRAME_MUXED_V_17_SEL_GPIO_IO_V_17          0x2
+#define PADFRAME_MUXED_V_17_SEL_HPC_CMD_EN            0x3
+#define PADFRAME_MUXED_V_17_SEL_SERIAL_LINK_O_V_3     0x4
 
 // Error codes
 #define EHOSTDEXEC 1 // Execution error host domain

sw/include/car_params.h

@@ -18,6 +18,8 @@ const void* car_l2_intl_0 = 0x78000000;
 const void* car_l2_cont_0 = 0x78010000;
 const void* car_l2_intl_1 = 0x78020000;
 const void* car_l2_cont_1 = 0x78030000;
+const void* fll = 0x21003000;
+const void* padframe = 0x21000000;
 
 #else // Pointers to be mapped by the driver
 void* car_soc_ctrl;
@@ -28,4 +30,6 @@ void* car_l2_intl_0;
 void* car_l2_cont_0;
 void* car_l2_intl_1;
 void* car_l2_cont_1;
+void* fll;
+void* padframe;
 #endif

sw/include/fll.h

@@ -0,0 +1,64 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Victor Isachi <[email protected]>
+//
+// FLL driver
+
+#ifndef __FLL_H
+#define __FLL_H
+
+#include "io.h"
+#include "car_memory_map.h"
+
+#define FLL_DCO_CODE_MASK (0x03FF0000)
+#define FLL_CLK_DIV_MASK  (0x3C000000)
+#define FLL_CLK_MUL_MASK  (0x0000FFFF)
+#define FLL_MODE_MASK     (0x80000000)
+
+#define FLL_DCO_CODE_OFFSET (16)
+#define FLL_CLK_DIV_OFFSET  (26)
+#define FLL_CLK_MUL_OFFSET  (0)
+#define FLL_MODE_OFFSET     (31)
+
+inline uint32_t set_bitfield(uint32_t val, uint32_t src_reg, uint32_t bitfield_mask, uint32_t bitfield_offset){
+  return (src_reg & ~bitfield_mask) | ((val << bitfield_offset) & bitfield_mask);
+}
+
+inline uint32_t read_fll_reg(uint8_t fll_id, uint8_t reg_offset){
+  return readw(FLL_BASE_ADDRESS(fll_id) + reg_offset);
+}
+
+inline void write_fll_reg(uint32_t val, uint8_t fll_id, uint8_t reg_offset){
+  writew(val, FLL_BASE_ADDRESS(fll_id) + reg_offset);
+}
+
+void write_fll_bitfield(uint32_t val, uint8_t fll_id, uint8_t reg_offset, uint32_t bitfield_mask, uint8_t bitfield_offset){
+  uint32_t fll_reg;
+  fll_reg = read_fll_reg(fll_id, reg_offset);
+  fll_reg = set_bitfield(val, fll_reg, bitfield_mask, bitfield_offset);
+  write_fll_reg(fll_reg, fll_id, reg_offset);
+}
+
+void fll_stand_alone(uint8_t fll_id){
+  write_fll_bitfield(0x0, fll_id, FLL_CONFIG_REG_I, FLL_MODE_MASK, FLL_MODE_OFFSET);
+}
+
+void fll_normal(uint8_t fll_id){
+  write_fll_bitfield(0x1, fll_id, FLL_CONFIG_REG_I, FLL_MODE_MASK, FLL_MODE_OFFSET);
+}
+
+void set_fll_dco_code(uint32_t dco_code, uint8_t fll_id){
+  write_fll_bitfield(dco_code, fll_id, FLL_CONFIG_REG_I, FLL_DCO_CODE_MASK, FLL_DCO_CODE_OFFSET);
+}
+
+void set_fll_clk_div(uint32_t clk_div, uint8_t fll_id){
+  write_fll_bitfield(clk_div, fll_id, FLL_CONFIG_REG_I, FLL_CLK_DIV_MASK, FLL_CLK_DIV_OFFSET);
+}
+
+void set_fll_clk_mul(uint32_t clk_mul, uint8_t fll_id){
+  write_fll_bitfield(clk_mul, fll_id, FLL_CONFIG_REG_I, FLL_CLK_MUL_MASK, FLL_CLK_MUL_OFFSET);
+}
+
+#endif /*__FLL_H*/

sw/include/padframe.h

@@ -0,0 +1,31 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Victor Isachi <[email protected]>
+//
+// Padframe driver
+
+#ifndef __PADFRAME_H
+#define __PADFRAME_H
+
+#include "io.h"
+#include "car_memory_map.h"
+
+inline void write_padframe_mux(uint8_t mux_sel_reg_offset, uint8_t mux_id){
+  writew(mux_id, PADFRAME_BASE_ADDRESS + mux_sel_reg_offset);
+}
+
+void write_padframe_pen(uint8_t cfg_reg_offset, uint8_t pen){
+  uint32_t config_reg = readw(PADFRAME_BASE_ADDRESS + cfg_reg_offset);
+  config_reg = (config_reg & ~0x8 ) | ((pen & 0x1) << 3);
+  writew(config_reg, PADFRAME_BASE_ADDRESS + cfg_reg_offset);
+}
+
+void write_padframe_psel(uint8_t cfg_reg_offset, uint8_t psel){
+  uint32_t config_reg = readw(PADFRAME_BASE_ADDRESS + cfg_reg_offset);
+  config_reg = (config_reg & ~0x10 ) | ((pen & 0x1) << 4);
+  writew(config_reg, PADFRAME_BASE_ADDRESS + cfg_reg_offset);
+}
+
+#endif /*__PADFRAME_H*/