Remove Thales IPs from default flow to be used on non-iis environment

* Remove them from bender manifest as they are still not benderized
* Add Make target to copy IPs from specific iis directory if needed
* Change Astral default configuration

Bender.yml

@@ -28,8 +28,6 @@ dependencies:
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,         version: 1.37.0                               } # branch: master
   pulp-ethernet:      { git: https://github.com/pulp-platform/pulp-ethernet.git,        rev: 2bea11658d2bc368ae2af0a3f71b4253ba4f713f } # branch: handshake
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg.git,            version: =0.8.0                               }
-  streamer:           { path: /usr/scratch2/lagrev5/mciani/astral-project/streamer  }
-  spacewire:          { path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire }
 
 workspace:
   package_links:
@@ -200,20 +198,6 @@ sources:
       - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v
       - target/xilinx/src/overrides/tc_clk_xilinx.sv
 
-  - target: intel16_elab_only
-    files:
-      # - tech/sourcecode/macros/sram_256x32.v
-      # - tech/sourcecode/macros/sram_128x40.v
-      # - tech/sourcecode/macros/sram_256x128.v
-      # - tech/sourcecode/macros/sram_256x44.v
-      # - tech/sourcecode/macros/sram_256x46.v
-      # - tech/sourcecode/tc_clk.sv
-      # - tech/sourcecode/tc_sram.sv
-      - nonfree/intel16/sourcecode/tc_clk.sv
-      - nonfree/intel16/sourcecode/tc_sram.sv
-      - nonfree/intel16/sourcecode/configurable_delay.sv
-      - nonfree/intel16/sourcecode/tc_sram_impl.sv
-      - nonfree/intel16/sourcecode/sync.sv
 
 vendor_package:
   - name: reggen

bender-common.mk

@@ -6,7 +6,7 @@
 # Author: Matteo Perotti <[email protected]>
 
 # Runtime-selectable Carfield configuration
-CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw
+CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_ethernet
 
 # bender targets
 common_targs += -t cva6

carfield.mk

@@ -63,6 +63,15 @@ car-nonfree-init:
 
 -include $(CAR_ROOT)/nonfree/nonfree.mk
 
+CAR_NONFREE_IPS += /usr/scratch2/lagrev5/mciani/astral-project/streamer
+CAR_NONFREE_IPS += /usr/scratch2/lagrev5/mciani/astral-project/spacewire
+
+## Clone the Thales IP for Astral. These IPs are not open-sourced and only available in
+## iis environment.
+car-nonfree-ips-init:
+	mkdir -p $(CAR_ROOT)/nonfreeips
+	cp -rf $(CAR_NONFREE_IPS) $(CAR_ROOT)/nonfreeips/
+
 #####################################
 # Islands' variables initialization #
 #####################################
@@ -103,10 +112,10 @@ SPATZD_BINARY   ?=
 SPATZD_BOOTMODE ?= 0 # default jtag bootmode
 
 # Streamer, implementing telecommand and telemetry protocols
-STREAMER_ROOT ?= $(shell $(BENDER) path streamer)
+STREAMER_ROOT ?= $(CAR_ROOT)/nonfreeips/streamer
 
 # SpaceWire IP
-SPACEWIRE_ROOT ?= $(shell $(BENDER) path spacewire)
+SPACEWIRE_ROOT ?= $(CAR_ROOT)/nonfreeips/spacewire
 
 # PLL/FLL bypass
 BYPASS_PLL ?= 0

target/sim/sim.mk

@@ -35,9 +35,6 @@ RUNTIME_DEFINES := +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)"
 RUNTIME_DEFINES += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\"
 RUNTIME_DEFINES += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\"
 
-TASI_LIB += vlib $ROOT/working_dir/streamer/TASI_generic_Lib
-TASI_LIB += vmap TASI_generic_Lib $ROOT/working_dir/streamer/TASI_generic_Lib
-
 #############
 # Questasim #
 #############
@@ -75,14 +72,16 @@ endif
 .PHONY: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl
 $(CAR_VSIM_DIR)/compile.carfield_soc.tcl:
 	$(BENDER) script vsim $(common_targs) $(sim_targs) $(sim_defs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@
+	echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
+	echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@
+ifeq ($(shell echo $(THALES_IPS)), 1)
 	sed -i '2a\
 	set VsimDir "$(CAR_VSIM_DIR)"\
 	set TCTMPATH "$(STREAMER_ROOT)"\
 	set SPWPATH "$(SPACEWIRE_ROOT)"\
 	source $(STREAMER_ROOT)/astral.compile.tcl \
 	source $(SPACEWIRE_ROOT)/astr_compile.tcl' $@
-	echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
-	echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@
+endif
 
 CAR_VSIM_ALL += $(CAR_SIM_ALL)
 CAR_VSIM_ALL += $(CAR_VSIM_DIR)/compile.carfield_soc.tcl

target/sim/src/vip_carfield_soc.sv

@@ -396,25 +396,29 @@ module vip_carfield_soc
   );
   */
 
-  tb_MuSA_compact i_tb_MuSA_compact (
-      .CADUClk    ( ptme_clk_i),
-      .CADUOut    ( ptme_enc_i),
-      .HPC_ADDR   ( hpc_addr_i),
-      .HPC_CMD_EN ( hpc_cmd_en_i),
-      .HPC_SMP    ( hpc_smp_i), 
-      .LLC_LINE   ( llc_line_i),
-      .RST_BOARD  ( rst_n),
-      .TCA        ( tc_active),
-      .TCC        ( tc_clk),
-      .TCS        ( tc_data)
-   );
-
-  spw_codec_tb i_spw_codec_tb (
-      .DATA_IN   (spw_din),
-      .STROBE_IN (spw_sin),
-      .DATA_OUT  (spw_dout),
-      .STROBE_OUT(spw_sout)
-   );
+  if (carfield_configuration::StreamerEnable) begin: gen_streamer_tb
+    tb_MuSA_compact i_tb_MuSA_compact (
+        .CADUClk    ( ptme_clk_i),
+        .CADUOut    ( ptme_enc_i),
+        .HPC_ADDR   ( hpc_addr_i),
+        .HPC_CMD_EN ( hpc_cmd_en_i),
+        .HPC_SMP    ( hpc_smp_i),
+        .LLC_LINE   ( llc_line_i),
+        .RST_BOARD  ( rst_n),
+        .TCA        ( tc_active),
+        .TCC        ( tc_clk),
+        .TCS        ( tc_data)
+    );
+  end
+
+  if (carfield_configuration::SpaceWireEnable) begin: gen_spw_tb
+    spw_codec_tb i_spw_codec_tb (
+        .DATA_IN   (spw_din),
+        .STROBE_IN (spw_sin),
+        .DATA_OUT  (spw_dout),
+        .STROBE_OUT(spw_sout)
+    );
+  end
 
 
 endmodule