Renamed I types to S types

propensive · Jun 20, 2024 · 217565c · 217565c
1 parent 933dfdd
commit 217565c
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Showing 6 changed files with 244 additions and 244 deletions.
diff --git a/src/core/hypotenuse-core.scala b/src/core/hypotenuse-core.scala
@@ -26,7 +26,7 @@ import scala.annotation.*
 import anticipation.*
 import contingency.*
 
-export Hypotenuse.{B8, B16, B32, B64, I8, I16, I32, I64, U8, U16, U32, U64, F32, F64}
+export Hypotenuse.{B8, B16, B32, B64, S8, S16, S32, S64, U8, U16, U32, U64, F32, F64}
 
 extension (float: Float)
   @targetName("absFloat")
@@ -383,13 +383,13 @@ package arithmeticOptions:
     inline given DivisionByZero as unchecked:
       type Wrap[ResultType] = ResultType
       inline def divideU64(left: U64, right: U64): U64 = U64((Long(left.bits)/Long(right.bits)).bits)
-      inline def divideI64(left: I64, right: I64): I64 = I64((left.long/right.long).bits)
+      inline def divideS64(left: S64, right: S64): S64 = S64((left.long/right.long).bits)
       inline def divideU32(left: U32, right: U32): U32 = U32((Int(left.bits)/Int(right.bits)).bits)
-      inline def divideI32(left: I32, right: I32): I32 = I32((left.int/right.int).bits)
+      inline def divideS32(left: S32, right: S32): S32 = S32((left.int/right.int).bits)
       inline def divideU16(left: U16, right: U16): U16 = U16((Short(left.bits)/Short(right.bits)).toShort.bits)
-      inline def divideI16(left: I16, right: I16): I16 = I16((left.short/right.short).toShort.bits)
+      inline def divideS16(left: S16, right: S16): S16 = S16((left.short/right.short).toShort.bits)
       inline def divideU8(left: U8, right: U8): U8 = U8((left.byte/right.byte).toByte.bits)
-      inline def divideI8(left: I8, right: I8): I8 = I8((left.byte/right.byte).toByte.bits)
+      inline def divideS8(left: S8, right: S8): S8 = S8((left.byte/right.byte).toByte.bits)
 
     inline given DivisionByZero as checked:
       type Wrap[ResultType] = ResultType raises DivisionError
@@ -398,41 +398,41 @@ package arithmeticOptions:
         if Long(right.bits) == 0 then raise(DivisionError())(U64(0.bits))
         else U64((Long(left.bits)/Long(right.bits)).bits)
 
-      inline def divideI64(left: I64, right: I64): I64 raises DivisionError =
-        if right.long == 0 then raise(DivisionError())(I64(0.bits)) else I64((left.long/right.long).bits)
+      inline def divideS64(left: S64, right: S64): S64 raises DivisionError =
+        if right.long == 0 then raise(DivisionError())(S64(0.bits)) else S64((left.long/right.long).bits)
 
       inline def divideU32(left: U32, right: U32): U32 raises DivisionError =
         if right.long == 0 then raise(DivisionError())(U32(0.bits))
         else U32((Int(left.bits)/Int(right.bits)).bits)
 
-      inline def divideI32(left: I32, right: I32): I32 raises DivisionError =
-        if right.int == 0 then raise(DivisionError())(I32(0.bits)) else I32((left.int/right.int).bits)
+      inline def divideS32(left: S32, right: S32): S32 raises DivisionError =
+        if right.int == 0 then raise(DivisionError())(S32(0.bits)) else S32((left.int/right.int).bits)
 
       inline def divideU16(left: U16, right: U16): U16 raises DivisionError =
         if right.int == 0 then raise(DivisionError())(U16(0.bits))
         else U16((Short(left.bits)/Short(right.bits)).toShort.bits)
 
-      inline def divideI16(left: I16, right: I16): I16 raises DivisionError =
-        if right.int == 0 then raise(DivisionError())(I16(0.bits))
-        else I16((left.short/right.short).toShort.bits)
+      inline def divideS16(left: S16, right: S16): S16 raises DivisionError =
+        if right.int == 0 then raise(DivisionError())(S16(0.bits))
+        else S16((left.short/right.short).toShort.bits)
 
       inline def divideU8(left: U8, right: U8): U8 raises DivisionError =
         if right.int == 0 then raise(DivisionError())(U8(0.bits)) else U8((left.byte/right.byte).toByte.bits)
 
-      inline def divideI8(left: I8, right: I8): I8 raises DivisionError =
-        if right.int == 0 then raise(DivisionError())(I8(0.bits)) else I8((left.byte/right.byte).toByte.bits)
+      inline def divideS8(left: S8, right: S8): S8 raises DivisionError =
+        if right.int == 0 then raise(DivisionError())(S8(0.bits)) else S8((left.byte/right.byte).toByte.bits)
 
   object overflow:
     inline given CheckOverflow as unchecked:
       type Wrap[ResultType] = ResultType
       inline def addU64(left: U64, right: U64): U64 = U64((Long(left.bits) + Long(right.bits)).bits)
-      inline def addI64(left: I64, right: I64): I64 = I64((left.long + right.long).bits)
+      inline def addS64(left: S64, right: S64): S64 = S64((left.long + right.long).bits)
       inline def addU32(left: U32, right: U32): U32 = U32((Int(left.bits) + Int(right.bits)).bits)
-      inline def addI32(left: I32, right: I32): I32 = I32((left.int + right.int).bits)
+      inline def addS32(left: S32, right: S32): S32 = S32((left.int + right.int).bits)
       inline def addU16(left: U16, right: U16): U16 = U16((Short(left.bits) + Short(right.bits)).toShort.bits)
-      inline def addI16(left: I16, right: I16): I16 = I16((left.short + right.short).toShort.bits)
+      inline def addS16(left: S16, right: S16): S16 = S16((left.short + right.short).toShort.bits)
       inline def addU8(left: U8, right: U8): U8 = U8((left.byte + right.byte).toByte.bits)
-      inline def addI8(left: I8, right: I8): I8 = I8((left.byte + right.byte).toByte.bits)
+      inline def addS8(left: S8, right: S8): S8 = S8((left.byte + right.byte).toByte.bits)
 
     inline given CheckOverflow as checked:
       type Wrap[ResultType] = ResultType raises OverflowError
@@ -443,8 +443,8 @@ package arithmeticOptions:
         if U64((left.bits^result) & (right.bits^result)) < U64(0.bits)
         then raise(OverflowError())(U64(result)) else U64(result)
 
-      inline def addI64(left: I64, right: I64): I64 raises OverflowError =
-        val result: I64 = I64((left.long + right.long).bits)
+      inline def addS64(left: S64, right: S64): S64 raises OverflowError =
+        val result: S64 = S64((left.long + right.long).bits)
         if result < left || result < right then raise(OverflowError())(result) else result
 
       inline def addU32(left: U32, right: U32): U32 raises OverflowError =
@@ -453,8 +453,8 @@ package arithmeticOptions:
         if U32((left.bits^result) & (right.bits^result)) < U32(0.bits)
         then raise(OverflowError())(U32(result)) else U32(result)
 
-      inline def addI32(left: I32, right: I32): I32 raises OverflowError =
-        val result: I32 = I32((left.int + right.int).bits)
+      inline def addS32(left: S32, right: S32): S32 raises OverflowError =
+        val result: S32 = S32((left.int + right.int).bits)
         if result < left || result < right then raise(OverflowError())(result) else result
 
       inline def addU16(left: U16, right: U16): U16 raises OverflowError =
@@ -463,8 +463,8 @@ package arithmeticOptions:
         if U16((left.bits^result) & (right.bits^result)) < U16(0.toShort.bits)
         then U16(raise(OverflowError())(result)) else U16(result)
 
-      inline def addI16(left: I16, right: I16): I16 raises OverflowError =
-        val result: I16 = I16((left.short + right.short).toShort.bits)
+      inline def addS16(left: S16, right: S16): S16 raises OverflowError =
+        val result: S16 = S16((left.short + right.short).toShort.bits)
         if result < left || result < right then raise(OverflowError())(result) else result
 
       inline def addU8(left: U8, right: U8): U8 raises OverflowError =
@@ -473,6 +473,6 @@ package arithmeticOptions:
         if U8((left.bits^result) & (right.bits^result)) < U8(0.toByte.bits)
         then U8(raise(OverflowError())(result)) else U8(result)
 
-      inline def addI8(left: I8, right: I8): I8 raises OverflowError =
-        val result: I8 = I8((left.short + right.short).toByte.bits)
+      inline def addS8(left: S8, right: S8): S8 raises OverflowError =
+        val result: S8 = S8((left.short + right.short).toByte.bits)
         if result < left || result < right then raise(OverflowError())(result) else result
diff --git a/src/core/hypotenuse.CheckOverflow.scala b/src/core/hypotenuse.CheckOverflow.scala
@@ -22,10 +22,10 @@ import language.experimental.into
 trait CheckOverflow:
   type Wrap[ResultType]
   inline def addU64(left: U64, right: U64): Wrap[U64]
-  inline def addI64(left: I64, right: I64): Wrap[I64]
+  inline def addS64(left: S64, right: S64): Wrap[S64]
   inline def addU32(left: U32, right: U32): Wrap[U32]
-  inline def addI32(left: I32, right: I32): Wrap[I32]
+  inline def addS32(left: S32, right: S32): Wrap[S32]
   inline def addU16(left: U16, right: U16): Wrap[U16]
-  inline def addI16(left: I16, right: I16): Wrap[I16]
+  inline def addS16(left: S16, right: S16): Wrap[S16]
   inline def addU8(left: U8, right: U8): Wrap[U8]
-  inline def addI8(left: I8, right: I8): Wrap[I8]
+  inline def addS8(left: S8, right: S8): Wrap[S8]
diff --git a/src/core/hypotenuse.DivisionByZero.scala b/src/core/hypotenuse.DivisionByZero.scala
@@ -21,10 +21,10 @@ import language.experimental.into
 trait DivisionByZero:
   type Wrap[ResultType]
   inline def divideU64(left: U64, right: U64): Wrap[U64]
-  inline def divideI64(left: I64, right: I64): Wrap[I64]
+  inline def divideS64(left: S64, right: S64): Wrap[S64]
   inline def divideU32(left: U32, right: U32): Wrap[U32]
-  inline def divideI32(left: I32, right: I32): Wrap[I32]
+  inline def divideS32(left: S32, right: S32): Wrap[S32]
   inline def divideU16(left: U16, right: U16): Wrap[U16]
-  inline def divideI16(left: I16, right: I16): Wrap[I16]
+  inline def divideS16(left: S16, right: S16): Wrap[S16]
   inline def divideU8(left: U8, right: U8): Wrap[U8]
-  inline def divideI8(left: I8, right: I8): Wrap[I8]
+  inline def divideS8(left: S8, right: S8): Wrap[S8]