fix for EDA-3310, map distributed mem to logic #177
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The RS FPGA architecture lacks distributed memory. Applying the attribute rom_style="distributed" in the design forces Yosys to map it to distributed memory, which is unavailable on this architecture. Therefore, the rom_style attribute has been changed to "logic" to map the memory onto LUTs/DFFs instead.
The test/batch_all has been tested in Raptor.