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build(deps): bump OpenFPGA from 53c155c to 27d2339 #747

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build(deps): bump OpenFPGA from 53c155c to 27d2339 #747

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2 changes: 1 addition & 1 deletion OpenFPGA
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Submodule OpenFPGA updated 76 files
+1 −1 VERSION.md
+3 −0 docs/source/manual/arch_lang/annotate_vpr_arch.rst
+117 −21 docs/source/manual/file_formats/clock_network.rst
+ − docs/source/manual/file_formats/figures/prog_clk_network_example_2x2.png
+11 −2 docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
+10 −8 libs/libarchopenfpga/src/read_xml_tile_annotation.cpp
+5 −0 libs/libarchopenfpga/src/tile_annotation.cpp
+2 −0 libs/libarchopenfpga/src/tile_annotation.h
+6 −6 libs/libclkarchopenfpga/arch/example.xml
+31 −0 libs/libclkarchopenfpga/arch/example_internal_drivers.xml
+350 −23 libs/libclkarchopenfpga/src/base/clock_network.cpp
+105 −17 libs/libclkarchopenfpga/src/base/clock_network.h
+4 −0 libs/libclkarchopenfpga/src/base/clock_network_fwd.h
+22 −5 libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h
+160 −21 libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
+88 −14 libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
+77 −8 libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp
+4 −0 libs/libclkarchopenfpga/src/utils/clock_network_utils.h
+4 −0 libs/libclkarchopenfpga/test/xml_io_clock_network.cpp
+158 −14 openfpga/src/annotation/append_clock_rr_graph.cpp
+45 −0 openfpga/src/annotation/openfpga_annotate_routing.cpp
+4 −0 openfpga/src/annotation/openfpga_annotate_routing.h
+420 −142 openfpga/src/annotation/route_clock_rr_graph.cpp
+7 −10 openfpga/src/annotation/route_clock_rr_graph.h
+7 −3 openfpga/src/base/openfpga_link_arch_template.h
+17 −3 openfpga/src/base/openfpga_read_arch_template.h
+6 −0 openfpga/src/base/openfpga_setup_command_template.h
+17 −9 openfpga/src/fabric/build_top_module_connection.cpp
+35 −0 openfpga/src/utils/openfpga_clustered_netlist_utils.cpp
+24 −0 openfpga/src/utils/openfpga_clustered_netlist_utils.h
+1 −1 openfpga_flow/openfpga_arch/k4_N4_40nm_Ntwk2clk2lvl_cc_openfpga.xml
+256 −0 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
+1 −0 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
+1 −1 openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga
+75 −0 openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+1 −1 openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
+6 −0 openfpga_flow/regression_test_scripts/basic_reg_test.sh
+32 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/clk_arch_1clk_1rst_2layer.xml
+8 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_reset.xml
+8 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/pin_constraints_resetb.xml
+4 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/repack_pin_constraints.xml
+54 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
+32 −0 ...ic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/clk_arch_1clk_1rst_2layer.xml
+8 −0 .../basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml
+8 −0 ...basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml
+4 −0 ...basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/repack_pin_constraints.xml
+54 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf
+40 −0 ...sts/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml
+8 −0 .../tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml
+8 −0 ...tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml
+4 −0 ...tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/repack_pin_constraints.xml
+54 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
+36 −0 ..._flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml
+8 −0 ...fpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_reset.xml
+8 −0 ...pga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/pin_constraints_resetb.xml
+4 −0 ...pga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/repack_pin_constraints.xml
+54 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf
+3 −3 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/clk_arch_1clk_2layer.xml
+1 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
+3 −3 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/clk_arch_1clk_2layer.xml
+1 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf
+4 −4 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
+0 −1 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/repack_constraints.xml
+1 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf
+18 −0 ...fpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml
+4 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/pin_constraints.xml
+4 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml
+41 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/task.conf
+18 −0 ...flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml
+4 −0 ...fpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/pin_constraints.xml
+4 −0 ...a_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml
+41 −0 openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/task.conf
+3 −3 openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml
+2 −2 openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml
+11 −1 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+1 −1 yosys
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