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    58 repositories

    • riscv-isa-manual

      Public
      RISC-V Instruction Set Manual
      TeX
      •
      Creative Commons Attribution 4.0 International
      •624•3.6k•188•15•Updated Sep 30, 2024Sep 30, 2024

    • riscv-smmtt

      Public
      This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      access-controltrusted-computingtrusted-execution-environmentconfidential-computingsmmttsupervisor-domainsap-tee
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •15•33•18•1•Updated Sep 30, 2024Sep 30, 2024

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •159•434•95•56•Updated Sep 30, 2024Sep 30, 2024

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •298•681•23•28•Updated Sep 30, 2024Sep 30, 2024

    • riscv-fast-interrupt

      Public
      Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •49•238•34•3•Updated Sep 30, 2024Sep 30, 2024

    • riscv-cheri

      Public
      This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      memory-safetycapabilitiescompartmentalization
      Python
      •
      Creative Commons Attribution 4.0 International
      •26•47•37•9•Updated Sep 30, 2024Sep 30, 2024

    • docs-dev-guide

      Public
      Documentation developer guide
      TeX
      •
      Creative Commons Attribution 4.0 International
      •30•81•2•0•Updated Sep 30, 2024Sep 30, 2024

    • riscv-docs-base-container-image

      Public
      A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      •6•8•0•3•Updated Sep 30, 2024Sep 30, 2024

    • riscv-performance-events

      Public
      RISC-V Performance Events Specification
      Python
      •
      Creative Commons Attribution 4.0 International
      •2•4•0•0•Updated Sep 27, 2024Sep 27, 2024

    • self-hosted-trace

      Public
      RISC-V Self-hosted Trace Development Fork
      TeX
      •
      Creative Commons Attribution 4.0 International
      •624•0•0•0•Updated Sep 27, 2024Sep 27, 2024

    • ft-trigger-delegation

      Public
      Trigger Delegation Fast-Track Specification
      TeX
      •
      Creative Commons Attribution 4.0 International
      •624•0•0•1•Updated Sep 26, 2024Sep 26, 2024

    • meta-riscv

      Public
      OpenEmbedded/Yocto layer for RISC-V Architecture
      riscvyocto-layeryoctoopenembeddedyocto-metaopenembedded-layerrisc-v
      BitBake
      •
      Other
      •136•358•17•0•Updated Sep 21, 2024Sep 21, 2024

    • riscv-zilsd

      Public
      Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•7•5•0•Updated Sep 18, 2024Sep 18, 2024

    • riscv-j-extension

      Public
      Working Draft of the RISC-V J Extension Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •17•162•7•3•Updated Sep 18, 2024Sep 18, 2024

    • riscv-debug-spec

      Public
      Working Draft of the RISC-V Debug Specification Standard
      Python
      •
      Other
      •92•454•50•1•Updated Sep 12, 2024Sep 12, 2024

    • configuration-structure

      Public
      RISC-V Configuration Structure
      Python
      •
      Creative Commons Attribution 4.0 International
      •15•36•8•0•Updated Sep 12, 2024Sep 12, 2024

    • riscv-spmp

      Public
      The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •7•11•2•0•Updated Sep 10, 2024Sep 10, 2024

    • riscv-glossary

      Public
      Makefile
      •4•5•10•0•Updated Sep 5, 2024Sep 5, 2024

    • riscv-control-transfer-records

      Public
      This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•15•2•0•Updated Sep 5, 2024Sep 5, 2024

    • riscv-profiles

      Public
      RISC-V Architecture Profiles
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •30•104•14•1•Updated Sep 5, 2024Sep 5, 2024

    • riscv-aia

      Public
      Creative Commons Attribution 4.0 International
      •18•72•22•4•Updated Aug 29, 2024Aug 29, 2024

    • riscv-double-trap

      Public
      RISC-V Double Trap Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•12•0•0•Updated Aug 23, 2024Aug 23, 2024

    • docs-spec-template

      Public template
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •19•18•1•1•Updated Aug 15, 2024Aug 15, 2024

    • docs-resources

      Public
      Creative Commons Attribution 4.0 International
      •13•21•2•1•Updated Aug 15, 2024Aug 15, 2024

    • composable-custom-extensions

      Public
      This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •0•1•1•0•Updated Jul 19, 2024Jul 19, 2024

    • riscv-dot-product

      Public
      Dot-Product Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•2•1•1•Updated Jul 16, 2024Jul 16, 2024

    • riscv-bfloat16

      Public
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •14•28•0•1•Updated Jul 9, 2024Jul 9, 2024

    • riscv-cfi

      Public
      This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •20•84•0•0•Updated Jul 9, 2024Jul 9, 2024

    • learn

      Public
      Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
      56•494•1•0•Updated Jul 4, 2024Jul 4, 2024

    • riscv-svvptc

      Public
      Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•2•1•0•Updated Jun 29, 2024Jun 29, 2024